80C451 Datasheet, PDF (7/22 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
Product specification
80C451/83C451/87C451
CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When
CSR.3 = 1, the positive edge of the ODS input clears the OBF flag.
When CSR.3 = 0, the negative edge of the ODS input clears the
OBF flag.
CSR.4, CSR.5 AFLAG Mode Select
(MA0, MA1) – Bits 4 and 5 select the mode of operation for the
AFLAG pin as follows:
MA1
0
0
1
1
MA0
0
1
0
1
AFLAG Function
Logic 0 output
Logic 1 output
OBF flag output (CSR.1)
Select (SEL) input mode
The select (SEL) input mode is used to determine whether the port 6
data register or the control status register is output on port 6. When
the select feature is enabled, the AFLAG input controls the source of
port 6 output data. A logic 0 on AFLAG input selects the port 6 data
register, and a logic 1 on AFLAG input selects the control status
register.
CSR.6, CSR.7 BFLAG Mode Select
(MB0, MB1) – Bits 6 and 7 select the mode operation as follows:
MB1 MB0
0
0
0
1
1
0
1
1
BFLAG Function
Logic 0 output
Logic 1 output
IBF flag output (CSR.0)
Port enable (PE)
In the port enable mode, IDS and ODS inputs are disabled when
BFLAG input is high. When the BFLAG input is low, the port is
enabled for I/O.
SPECIAL FUNCTION REGISTER ADDRESSES
The SFRs are identical to those of the standard 80C51 with the
exception of four registers that have been added to allow control of
the three additional I/O ports P4, P5, and P6. The additional
registers are P4, P5, P6, and CSR. Registers P4, P5, and P6
function as port latches for ports 4, 5, and 6, respectively. These
registers operate identically to those for ports 0 through 3 of the
80C51.
Table 1. Special Function Register Addresses
REGISTER ADDRESS
NAME
SYMBOL
Port 4
Port 5
Port 6 data
Port 6 control status
P4
P5
P6
CSR
ADDRESS
C0
C8
D8
E8
BIT ADDRESS
MSB
LSB
C7 C6 C5 C4 C3 C2 C1 C0
CF CE CD CC CB CA C9 C8
DF DE DD DC DB DA D9 D8
EF EE ED EC EB EA E9 E8
AFLAG BFLAG ODS
PORT 6
BFLAG/ODS
MODE
(CSR.6/.7)
AFLAG
MODE
(CSR.4/.5)
INPUT BUFFER
FULL (CSR.0)
OUTPUT
DRIVERS
MUX
IDS
INPUT
BUFFER
(P6 READ)
IDS
MODE
EDGE/LEVEL
SELECT (CSR.2)
OUTPUT BUFFER
FULL (CSR.1)
CONTROL/STATUS
REGISTER (CSR)
OUTPUT BUFFER
(P6 WRITE)
INTERNAL BUS
Figure 1. Port 6 Block Diagram
SU00087
1998 May 01
7