80C451 Datasheet, PDF (11/22 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
Product specification
80C451/83C451/87C451
AC ELECTRICAL CHARACTERISTICS¹
T_amb = 0°C to +70°C, V_CC = 5V ±10%, V_SS = 0V (87C451, 83C451, 80C451)²
12MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
1/t_CLCL
Oscillator frequency:
SC8XC451
SC8XC451
Speed Versions
C
G
t_LHLL
2
t_AVLL
2
t_LLAX
2
t_LLIV
2
t_LLPL
2
t_PLPH
2
t_PLIV
2
t_PXIX
2
t_PXIZ
2
t_AVIV
2
t_PLAZ
2
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
127
28
48
234
43
205
145
0
59
312
10
t_RLRH
3, 4
t_WLWH
3, 4
t_RLDV
3, 4
t_RHDX
3, 4
t_RHDZ
3, 4
t_LLDV
3, 4
t_AVDV
3, 4
t_LLWL
3, 4
t_AVWL
3, 4
t_QVWX
3, 4
t_WHQX
3, 4
t_RLAZ
3, 4
t_WHLH
3, 4
Shift Register
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
400
400
252
0
97
517
585
200
300
203
23
33
0
43
123
t_XLXL
5
Serial port clock cycle time
t_QVXH
5
Output data setup to clock rising edge
t_XHQX
5
Output data hold after clock rising edge
t_XHDX
5
Input data hold after clock rising edge
t_XHDV
5
Clock rising edge to input data valid
NOTES: SEE NEXT PAGE
1.0
700
50
0
700
VARIABLE CLOCK
MIN
MAX
UNIT
3.5
3.5
2t_CLCL–40
t_CLCL–55
t_CLCL–35
t_CLCL–40
3t_CLCL–45
0
12
16
4t_CLCL–100
3t_CLCL–105
t_CLCL–25
5t_CLCL–105
10
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6t_CLCL–100
ns
6t_CLCL–100
ns
5t_CLCL–165
ns
0
ns
2t_CLCL–70
ns
8t_CLCL–150
ns
9t_CLCL–165
ns
3t_CLCL–50
3t_CLCL+50
ns
4t_CLCL–130
ns
t_CLCL–60
ns
t_CLCL–50
ns
0
ns
t_CLCL–40
t_CLCL+40
ns
12t_CLCL
µs
10t_CLCL–133
ns
2t_CLCL–117
ns
0
ns
10t_CLCL–133
ns
1998 May 01
11