74F595 Datasheet, PDF (7/13 Pages) NXP Semiconductors – 8-bit shift register with output laches 3-State

Philips Semiconductors
8-bit shift register with output latches (3-State)
Product specification
74F595
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
f_MAX
t_PLH
t_PHL
t_PLH
t_PHL
t_PHL
t_PZH
t_PZL
t_PHZ
t_PLZ
Maximum clock frequency–SHCP to Qs
Propagation delay
SHCP to Qs
Propagation delay
STCP to Q0–Q7
Propagation delay
SHR to Qs
Output Enable time
OE to Q0–Q7
Output Disable time
OE to Q0–Q7
AC SETUP REQUIREMENTS
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform 5
Waveform 6
Waveform 5
Waveform 6
SYMBOL
PARAMETER
TEST
CONDITION
t_s(H)
t_s(L)
t_h(H)
t_h(L)
t_s(L)
t_s(H)
t_W(H)
t_W(L)
t_W(H)
t_W(L)
t_W(L)
t_REC
Setup time, High or Low
Ds to SHCP
Hold time, High or Low
Ds to SHCP
Setup time, Low
SHR to STCP
Setup time, High
SHCP to STCP
SHCP Pulse width,
High or Low
STCP Pulse width,
High or Low
SHR Pulse width, Low
Recovery time,
SHR to SHCP
Waveform 3
Waveform 3
Waveform 3
Waveform 4
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
LIMITS
V_CC = +5V
T_amb = +25°C
C_L = 50pF, R_L = 500Ω
V_CC = +5V ± 10%
T_amb = 0°C to +70°C
C_L = 50pF, R_L = 500Ω
MIN TYP MAX
MIN
MAX
115 135
90
6.0
8.0 10.5
5.0
12.5
2.5
4.5
7.5
2.5
7.5
5.5
8.0 10.0
4.5
13.0
3.0
5.0
8.0
3.0
8.5
3.5
5.5
8.0
3.0
8.5
3.5
5.5
9.0
2.5
10.5
3.0
5.5
8.5
2.5
10.5
2.0
4.0
7.0
1.5
8.5
4.0
6.0
9.0
3.0
10.5
LIMITS
V_CC = +5V
T_amb = +25°C
C_L = 50pF, R_L = 500Ω
MIN TYP MAX
V_CC = +5V ± 10%
T_amb = 0°C to +70°C
C_L = 50pF, R_L = 500Ω
MIN
MAX
2.0
2.5
2.0
2.5
0
0
0
0
4.5
5.0
4.5
5.0
3.5
4.0
4.0
4.0
4.0
4.0
3.0
3.5
3.0
3.0
3.0
3.0
AC WAVEFORMS
For all waveforms, V_M = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
UNIT
MHz
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
1990 Apr 18
7