74F573 Datasheet, PDF (7/14 Pages) NXP Semiconductors – Octal transparent latch 3-State

Philips Semiconductors
Latch/flip-flop
Product specification
74F573/74F574
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITIONS
t_PLH
t_PHL
t_PLH
t_PHL
t_PZH
t_PZL
t_PHZ
t_PLZ
f_MAX
t_PLH
t_PHL
t_PZH
t_PZL
t_PHZ
t_PLZ
Propagation delay
Dn to Qn
Propagation delay
E to Qn
Output Enable time
to High or Low level
74F573
Output Disable time
from High or Low level
Maximum Clock frequency
Propagation delay
CP to Qn
Output Enable time
to High or Low level
74F574
Output Disable time
from High or Low level
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
LIMITS
T_amb= +25°C
V_CC = +5V
C_L = 50pF, R_L = 500Ω
MIN
TYP MAX
T_amb = 0°C to +70°C
V_CC = +5V ± 10%
C_L = 50pF, R_L = 500Ω
MIN
MAX
3.0
5.5
8.0
2.5
9.0
1.0
3.5
6.0
1.0
7.0
4.5
8.5
11.5
4.0
12.5
3.0
5.0
7.0
2.5
8.0
2.5
5.5
9.5
2.0
10.5
2.5
5.5
8.0
2.0
8.5
1.0
3.0
6.0
1.0
6.5
1.0
2.5
5.5
1.0
5.5
160
180
150
3.5
5.0
7.5
3.0
8.0
3.5
5.0
7.5
3.0
8.0
2.5
4.5
7.5
2.0
7.5
3.0
5.0
8.0
3.0
8.5
1.0
3.0
5.5
1.0
6.0
1.0
2.5
5.5
1.0
6.0
UNIT
ns
ns
ns
ns
MHz
ns
ns
ns
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
TEST
CONDITIONS
t_s(H)
t_s(L)
t_h(H)
t_h(L)
t_w(H)
t_s(H)
t_s(L)
t_h(H)
t_h(L)
t_w(H)
t_w(L)
Setup time,
Dn to E
Hold time,
Dn to E
E pulse width,
High
Setup time,
Dn to CP
Hold time,
Dn to CP
CP Pulse width,
High or Low
Waveform 4
74F573
Waveform 4
Waveform NO TAG
Waveform NO TAG
74F574 Waveform NO TAG
Waveform NO TAG
LIMITS
T_amb= +25°C
V_CC = +5V
C_L = 50pF, R_L = 500Ω
MIN
TYP
MAX
T_amb = 0°C to +70°C
V_CC = +5.0V ± 10%
C_L = 50pF, R_L = 500Ω
MIN
MAX
0.0
0.0
1.5
2.0
2.5
2.5
4.0
4.0
3.0
3.5
2.5
3.0
2.5
3.0
0
0
0
0
3.0
3.0
3.5
4.0
UNIT
ns
ns
ns
ns
ns
ns
1989 Oct 16
7