74F573 Datasheet, PDF (4/14 Pages) NXP Semiconductors – Octal transparent latch 3-State

Philips Semiconductors
Latch/flip-flop
Product specification
74F573/74F574
LOGIC DIAGRAM – 74F573
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
D
EQ
E ¹¹
1
OE
V_CC=Pin 20
GND=Pin 10
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SF01079
FUNCTION TABLE – 74F573
INPUTS
OE
E
Dn
INTERNAL
REGISTER
OUTPUTS
Q0 – Q7
L
H
L
L
L
L
H
H
H
H
L
↓
l
L
L
L
↓
h
H
H
L
L
X
NC
NC
H
L
X
NC
Z
H
H
Dn
Dn
Z
H = High voltage level
h = High voltage level one setup time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one setup time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low E transition
OPERATING MODES
Load and read register
Latch and read register
Hold
Disable outputs
LOGIC DIAGRAM – 74F574
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
CP ¹¹
1
OE
V_CC=Pin 20
GND=Pin 10
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SF01080
1989 Oct 16
4