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ISP1561 Datasheet, PDF (57/102 Pages) NXP Semiconductors – ISP1561BM | |||
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Philips Semiconductors
ISP1561
USB PCI host controller
Table 78: HcRhDescriptorA register: bit allocation
Bit
31
30
29
Symbol
Reset
1
1
1
Access
R/W
R/W
R/W
Bit
23
22
21
Symbol
Reset
0
0
0
Access
-
-
-
Bit
15
14
13
Symbol
reserved
Reset
0
0
0
Access
-
-
-
Bit
7
6
5
Symbol
Reset
0
0
0
Access
R
R
R
28
27
POTPGT[7:0]
1
1
R/W
R/W
20
19
reserved
0
0
-
-
12
11
NOCP
OCPM
0
1
R/W
R/W
4
3
NDP[7:0]
0
0
R
R
[1] X is 1 for OHCI1 (2P) and OHCI2 (2P); X is 0 for OHCI1 (1P) and OHCI2 (1P).
[2] X is 0 for OHCI1 (2P) and OHCI2 (2P); X is 1 for OHCI1 (1P) and OHCI2 (1P).
26
1
R/W
18
0
-
10
DT
0
R
2
0
R
25
1
R/W
17
0
-
9
NPS
0
R/W
1
X[1]
R
24
1
R/W
16
0
-
8
PSM
1
R/W
0
X[2]
R
Table 79: HcRhDescriptorA register: bit description
Bit
Symbol
Description
31 to 24
POTPGT[7:0]
PowerOnToPowerGoodTime: This byte speciï¬es the
duration HCD has to wait before accessing a powered-on port
of the Root Hub. It is implementation-speciï¬c. The unit of time
is 2 ms. The duration is calculated as POTPGT Ã 2 ms.
23 to 13 -
reserved
12
NOCP
NoOverCurrentProtection: This bit describes how the
overcurrent status for Root Hub ports are reported. When this
bit is cleared, the OCPM (OverCurrentProtectionMode) ï¬eld
speciï¬es global or per-port reporting.
11
OCPM
0 â overcurrent status is reported collectively for all
downstream ports
1 â no overcurrent protection supported
OverCurrentProtectionMode: This bit describes how the
overcurrent status for Root Hub ports are reported. At reset,
this ï¬elds reï¬ects the same mode as PowerSwitchingMode.
This ï¬eld is valid only if the NOCP ï¬eld is cleared.
10
DT
0 â overcurrent status is reported collectively for all
downstream ports
1 â overcurrent status is reported on a per-port basis
DeviceType: This bit speciï¬es that the Root Hub is not a
compound device. The Root Hub is not permitted to be a
compound device. This ï¬eld should always read 0.
9397 750 10015
Product data
Rev. 01 â 06 February 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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