ISP1561 Datasheet, PDF (17/102 Pages) NXP Semiconductors – ISP1561BM

Philips Semiconductors
ISP1561
USB PCI host controller
Command register (address: 04H): This is a two-byte register that provides coarse
control over the ability of a device to generate and respond to PCI cycles. The bit
allocation of the Command register is given in Table 6. When logic 0 is written to this
register, the device is logically disconnected from the PCI bus for all accesses except
configuration accesses. All devices are required to support this base level of
functionality. Individual bits in the Command register may or may not support this
base level of functionality.
Table 6: Command register: bit allocation
Bit
15
14
13
12
11
Symbol
reserved
Reset
0
0
0
0
0
Access
-
-
-
-
-
Bit
7
6
5
4
3
Symbol
SCTRL
PER
VGAPS
MWIE
SC
Reset
0
0
0
0
0
Access
R
R/W
R
R/W
R
10
9
8
FBBE
SERRE
0
0
0
-
R/W
R/W
2
1
0
BM
MS
IOS
0
0
0
R/W
R/W
R/W
Table 7:
Bit
15 to 10
9
Command register: bit description
Symbol Description
-
reserved
FBBE
Fast Back-to-Back Enable: This bit controls whether or not a
master can do fast back-to-back transactions to different devices.
The initialization software needs to set this bit if all targets are fast
back-to-back capable.
0 — fast back-to-back transactions are only allowed to the same
agent (value after RST#)
1 — the master is allowed to generate fast back-to-back
transactions to different agents
8
SERRE SERR# Enable: This bit is an enable bit for the SERR# driver. All
devices that have an SERR# pin must implement this bit. Address
parity errors are reported only if this bit and the PER bit are logic 1.
0 — disable the SERR# driver
1 — enable the SERR# driver
7
SCTRL
Stepping Control: This bit is used to control whether or not a
device does address and data stepping. Devices that never do
stepping must clear this bit. Devices that always do stepping must
set this bit. Devices that can do either, must make this bit
read/write and have it initialize to logic 1 after RST#.
6
PER
Parity Error Response: This bit controls the response of a device
to parity errors. When the bit is set, the device must take its normal
action when a parity error is detected. When the bit is logic 0, the
device sets its Detected Parity Error status bit (bit 15 in the Status
register) when an error is detected, but does not assert PERR#
and continues normal operation. The state of this bit after RST# is
logic 0. Devices that check parity must implement this bit. Devices
are required to generate parity even if parity checking is disabled.
9397 750 10015
Product data
Rev. 01 — 06 February 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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