ISP1561 Datasheet, PDF (43/102 Pages) NXP Semiconductors – ISP1561BM

Philips Semiconductors
ISP1561
USB PCI host controller
Table 48: HcInterruptStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
OC
reserved
Reset
0
0
0
0
0
0
0
0
Access
-
R/W
-
-
-
-
-
-
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
0
0
0
0
0
0
0
0
Access
-
-
-
-
-
-
-
-
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
0
0
0
0
0
0
0
0
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
Reset
0
0
0
0
0
0
0
0
Access
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 49: HcInterruptStatus register: bit description
Bit
Symbol Description
31
−
reserved
30
OC
OwnershipChange: This bit is set by the Host Controller when
HCD sets the OCR (OwnershipChangeRequest) field in
HcCommandStatus. This event, when unmasked, will always
generate a System Management Interrupt (SMI) immediately. This
bit is forced to 0 when the SMI# pin is not implemented.
29 to 7
-
reserved
6
RHSC
RootHubStatusChange: This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
5
FNO
FrameNumberOverflow: This bit is set when the MSB of
HcFmNumber (bit 15) changes value, or after the
HccaFrameNumber has been updated.
4
UE
UnrecoverableError: This bit is set when the Host Controller
detects a system error not related to USB. The Host Controller
should not proceed with any processing nor signaling before the
system error has been corrected. The HCD clears this bit after the
Host Controller has been reset.
3
RD
ResumeDetected: This bit is set when the Host Controller detects
that a device on the USB is asserting resume signaling. It is the
transition from no resume signaling to resume signaling causing
this bit to be set. This bit is not set when the HCD sets the
USBRESUME state.
9397 750 10015
Product data
Rev. 01 — 06 February 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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