P8XCX70 Datasheet, PDF (52/80 Pages) NXP Semiconductors – Fully static 80C51 CPU

Philips Semiconductors
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
Product specification
P8xCx70 family
18.9 Register descriptions
All registers are read/writeable. When the registers are read a value will be returned that will correspond to the written
data. There is one exception; when the Status Register is read, status information will be returned.
18.9.1 DISPLAY CONTROL REGISTER (DCR)
Table 75 Display Control Register (address 87F0H)
7
6
5
4
3
SRC3
SRC2
SRC1
SRC0
FLF
2
MSH
1
MOD1
B0
MOD0
Table 76 Description of DCR bits
BIT
SYMBOL
DESCRIPTION
7
SCR3 Screen colour. These 4 bits select the screen colour; one of 16 colours may be
6
SCR2 ^{selected; see Table 59.}
5
SCR1
4
SCR0
3
FLF
Flash frequency. The state of this bit determines the flash frequency of the screen.
A frequency of 1 or 2 Hz can be selected; see Table 60.
2
MSH Meshing. If MSH = 1, meshing is selected. See Section 18.2.12.
1
MOD1 Display modes. These 2 bits select one of the four display modes: Video mode, Full
0
MOD0 ^{Text mode, Mixed Screen mode and Mixed Video mode; see Table 56.}
18.9.2 TEXT VERTICAL POSITION REGISTER (TVPR)
Table 77 Text Vertical Position Register (address 87F1H)
7
VPOL
6
HPOL
5
VOL5
4
VOL4
3
VOL3
VOL2
1
VOL1
0
VOL0
Table 78 Description of TVPR bits
BIT
SYMBOL
DESCRIPTION
7
VPOL Vertical sync polarity. The state of this bit determines whether the vertical sync input is
inverted or not; see Table 74.
6
HPOL Horizontal sync polarity. The state of this bit determines whether the horizontal sync
input is inverted or not; see Table 74.
5
VOL5 Vertical offset. These 6 bits select the number of lines that the text area is offset
4
VOL4 ^{vertically; see Table 72.}
3
VOL3
2
VOL2
1
VOL1
0
VOL0
1999 Jun 11
52