P8XCX70 Datasheet, PDF (20/80 Pages) NXP Semiconductors – Fully static 80C51 CPU

Philips Semiconductors
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
Product specification
P8xCx70 family
11 INTERRUPT SYSTEM
The P8xCx70 has seven interrupt sources, each of which
can be assigned one of two priority levels as shown in
Fig.7. The four interrupt sources common to the 80C51 are
the external interrupts (INT0 and INT1) and the Timer 0
and Timer 1 interrupts. The SIO1 (I²C-bus) interrupt is
generated by the S1 flag in the Serial Control Register
(S1CON). This flag is set when SFR S1STA is loaded with
a valid status code. The CC interrupt is generated by the
RCC flag in SFR IRQ1; this flag is set at the end of the
selected CVBS slice line. The BUSY interrupt is generated
by the RBUSY flag which also resides in SFR IRQ1 and is
set by the OSD.
11.1 How interrupts are handled
The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following
machine cycle. If one of the flags was in a set condition at
S5P2 of the preceding cycle, the polling cycle will find it
and the interrupt system will generate a LCALL to the
appropriate service routine, provided that LCALL is not
blocked by any of the following conditions:
1. An interrupt of equal priority or higher priority level is
already in progress.
2. The current machine cycle is not the final cycle in the
execution of the instruction in progress (no interrupt
request will be serviced until the instruction in progress
is completed).
3. The instruction in progress is RETI or any access to
the interrupt priority or interrupt enable registers (no
interrupt will be serviced after RETI or after a read or
write to IP0, IP1, IEN0 or IEN1 until at least one other
instruction has been subsequently executed).
The polling cycle is repeated with each machine cycle, and
the values polled are the values that were present at S5P2
of the previous machine cycle. Note that if an interrupt flag
is active but not being responded to for one of the above
mentioned conditions, if the flag is still inactive when the
blocking condition is removed, the denied interrupt will not
be serviced. In other words, the fact that the interrupt flag
was once active but not serviced is not remembered.
Every polling cycle is new.
Note that if an interrupt of higher priority level becomes
active prior to S5P2 of the machine cycle labelled C3, then
in accordance with the rules it will be vectored to during
C5 and C6, without any instruction of the lower priority
routine having been executed. Thus the processor
acknowledges an interrupt request by executing a
hardware generated LCALL to the appropriate servicing
routine. The hardware generated LCALL pushes the
contents of the Program Counter on to the stack (but does
not save the PSW) and reloads the PC with an address
that depends on the source of the interrupt; see Table 20.
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that the interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
Note that a simple RET instruction would also return
execution to the interrupted program, but it would have left
the interrupt control system thinking an interrupt was still in
progress, making future interrupts impossible.
Table 20 Interrupt vectors
SOURCE
INT0
I²C-bus
Timer 0
INT1
BUSY
Timer 1
CC
VECTOR ADDRESS
0003H
002BH
000BH
0013H
0063H
001BH
006BH
Additional details on the interrupt operation are given in
“Data Handbook IC20, 80C51-Based 8-bit
Microcontrollers”.
1999 Jun 11
20