UMA1022M Datasheet, PDF (5/20 Pages) NXP Semiconductors – Low cost dual frequency synthesizer for radio telephones

Philips Semiconductors
Low cost dual frequency synthesizer for
radio telephones
Product specification
UMA1022M
FUNCTIONAL DESCRIPTION
Main dividers
The main dividers are clocked at pin RF_A by the RF
oscillator signal and at pin IF_B by the IF oscillator signal.
The inputs are AC coupled through external capacitors.
Input impedances are high, dominated by parasitic
package capacitances, so matching is off-chip.
The sensitive dividers operate with signal levels from
35 to 225 mV (RMS), at frequencies up to 2.1 GHz
(RF part) and up to 550 MHz (IF part). Both include
programmable bipolar prescalers followed by CMOS
counters. The RF main divider allows programmable ratios
from 512 to 65535; the IF blocks accept values between
128 and 16383.
Crystal oscillator
A fully differential low-noise amplifier/buffer is integrated
providing outputs to drive other circuits, and to build a
crystal oscillator; only needed are an external resonance
circuit and tuning elements (temperature compensation).
A bus controlled power-down mode disables the low-noise
amplifier to reduce current if not needed.
The normal differential input pins drive a clock buffer to
provide edges to the programmable reference divider at
frequencies up to 20 MHz. The inputs are AC coupled
through external capacitors, and operate with signals
down to 35 mV (RMS) and up to 0.5 V (RMS).
Various crystal oscillator structures can be built using the
amplifier. By coupling one output back to the appropriate
input through the resonator, and decoupling the other input
to ground, the second output becomes available to deliver
the reference frequency to other circuits.
Reference dividers
A first common divider circuit produces an output
frequency for RF or IF synthesizer phase comparison,
depending on the P/A bit. It drives a second independent
divider, which delivers the reference edge to the IF or RF
synthesizer phase comparator. When P/A is logic 1, the
output of the subdivider is connected to the RF phase
comparator, whereas the output of the common divider is
connected to the IF phase detector.
The phase comparators run at related frequencies with a
controlled phase difference to avoid interference when
in-lock. The common 10-bit section permits divide ratios
from 8 to 1023; the second subdivider allows phase
comparison frequency ratios between 1 and 16. Table 2
indicates how to program the corresponding bits to get the
wanted ratio.
Phase comparators
The phase detectors are driven by the output edges
selected by the main and reference dividers. Each
generates lead and lag signals to control the appropriate
charge pump. The pumps output current pulses appear at
pins CP_A (RF synthesizer) and CP_B (IF synthesizer).
The current pulse duration is at least equal to the
difference in time of arrival of the edges from the two
dividers. If the main divider edge arrives first, CP_A or CP_B
sink current. If the reference divider edge arrives first, CP_A
or CP_B source current. For correct PLL operation the
VCOs need to have a positive frequency/voltage control
slope.
The currents at CP_A and CP_B are programmed via the
serial bus as multiples of an internally-set reference
current. The passage into power-down mode is
synchronized with respect to the phase detector to prevent
output current pulses being interrupted. Additional circuitry
is included to ensure that the gain of the phase
comparators remains linear even for small phase errors.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, clock (CLK) and enable
(E). The data sent to the device is loaded in bursts framed
by E. Programming clock edges and their appropriate data
bits are ignored until E goes active LOW. The programmed
information is loaded into the addressed latch when E
returns HIGH. During normal operation, E should be kept
HIGH. Only the last 19 bits serially clocked into the device
are retained within the programming register.
Additional leading bits are ignored, and no check is made
on the number of clock pulses. The NMOS-rich design
uses virtually no current when the bus is inactive;
power-up is initiated when enable is taken LOW, and
power-down occurs a short time after enable returns
HIGH. Bus activity is allowed when either synthesizer is
active or in power-down (ON_A and ON_B inputs LOW)
mode. Fully static CMOS registers retain programmed
data whatever the power-down state, as long as the supply
voltage is present.
1998 Dec 09
5