UMA1021M Datasheet, PDF (5/16 Pages) NXP Semiconductors – Low-voltage frequency synthesizer for radio telephones

Philips Semiconductors
Low-voltage frequency synthesizer
for radio telephones
Product specification
UMA1021M
Phase detector
The phase detector is driven by the output edges of the
main and reference dividers. It produces current pulses at
pins CP and CPF whose amplitudes are programmed.
The pulse duration is equal to the difference in time of
arrival of the edges from the two dividers. If the main
divider edge arrives first, CP and CPF sink current. If the
reference divider edge arrives first, CP and CPF source
current.
The currents at CP and CPF are programmed via the serial
bus as multiples of a reference current set by an external
resistor connected between pin I_SET and V_SS
(see Table 3). CP remains active except in power-down.
CPF is enabled via input pin FAST which is synchronized
with respect to the phase detector to prevent output
current pulses being interrupted. By appropriate
connection to the loop filter, dual bandwidth loops can be
designed; short time constant during frequency switching
(FAST mode) to speed-up channel changes, and low
bandwidth in the settled state to improve noise and
breakthrough levels.
Additional circuitry is included to ensure that the gain of the
phase detector remains linear even for small phase errors.
Out-of-lock detector
The out-of-lock detector is enabled (disabled) via the serial
interface by setting bit OOL HIGH (LOW). An open drain
transistor drives the output pin LOCK (pin 20). It is
recommended that the pull-up resistor from this pin to V_DD
is chosen to be of sufficient value to keep the sink current
in the LOW state to below 400 µA. When the out-of-lock
detector is enabled, LOCK is HIGH if the error at the phase
detector input is less than approximately 25 ns, otherwise
LOCK is LOW. If the out-of-lock detector is disabled,
LOCK remains HIGH.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, clock (CLK) and enable
(E). The data sent to the device is loaded in bursts framed
by E. Programming clock edges and their appropriate data
bits are ignored until E goes active LOW. The programmed
information is loaded into the addressed latch when E
returns HIGH.
During normal operation, E should be kept HIGH. Only the
last 21 bits serially clocked into the device are retained
within the programming register. Additional leading bits
are ignored, and no check is made on the number of clock
pulses. The fully static CMOS design uses virtually no
current when the bus is inactive. It can always capture new
programmed data even during power-down.
When the synthesizer is powered-on, the presence of a
TCXO signal at the reference divider input and a VCO
signal at the main divider input is required for correct
programming.
Data format
The leading bits (dt16 to dt0) make up the data field, while
the trailing four bits (ad3 to ad0) are the address field.
The UMA1021M uses 4 of the 16 available addresses.
These are chosen for compatibility with other Philips
Semiconductors radio telephone ICs. The data format is
shown in Table 1. The first bit entered is dt16, the last bit
is ad0. For the divider ratios, the first bits entered (PM16
and PR10) are the most significant (MSB).
The trailing address bits are decoded on the rising edge of
E. This produces an internal load pulse to store the data in
the addressed latch. To avoid erroneous divider ratios,
the load pulse is not allowed during data reads by the
frequency dividers. This condition is guaranteed by
respecting a minimum E pulse width after data transfer.
The test register (address 0000) does not normally need to
be programmed. However if it is programmed, all bits in the
data field should be set to logic 0.
Power-down mode
The synthesizer is on when both the input signals PON
and the programmed bit sPON are active. The ‘active’ level
for these two signals is chosen at pin POL (see Table 2).
When turned on, the dividers and phase detector are
synchronized to avoid random phase errors. When turned
off, the phase detector is synchronized to avoid
interrupting charge-pump pulses. For synchronisation
functions to work correctly on power-up or power-down
(using either hardware or software programming), the
presence of TCXO and VCO signals is required to drive
the appropriate divider inputs. The UMA1021M has a very
low current consumption in the power-down mode.
1999 Jun 17
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