PHT6N03LT Datasheet, PDF (5/6 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT6N03LT
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2%
typ
98%
1E-04
1E-05
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
C / pF
10000
9528-30
Ciss
1000
Coss
Crss
100
0.1
1
10
100
VDS / V
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
VGS / V
5
4
VDS / V = 6
9830-30
24
3
2
1
0
0
5
10
15
20
25
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); conditions: I_D = 5.9 A; parameter V_DS
60 ^{IF / A}
9830-30
50
40
30
Tj / C = 150
25
20
10
0
0
0.5
1
1.5
2
VSDS / V
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20
40
60
80 100 120 140
Ambient temperature, Tamb (C)
Fig.15. Normalised avalanche energy rating.
W_DSS% = f(T_amb); conditions: I_D = 5.9 A
VGS
0
RGS
L
VDS
T.U.T.
+ ^VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
W_DSS = 0.5 ⋅ LI_D² ⋅ BV_DSS/(BV_DSS − V_DD)
January 1998
5
Rev 1.300