PHT6N03LT Datasheet, PDF (4/6 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT6N03LT
ID / A
60
10
5
6
50
40
30
VGS / V =
BUK9830-30
4.5
4
3.5
20
3
10
2.5
0
0
2
4
6
8
10
VDS / V
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
RDS(ON) / mOhm
60
3
50
9830-30
3.5
4
40
4.5
30
5
20
10
6
VGS / V =
10
0
0
10
20
30
40
50
60
ID / A
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
ID / A
60
9830-30
50
Tj / C = 25
40
150
30
20
10
0
0
1
2
3
4
5
6
VGS / V
Fig.7. Typical transfer characteristics.
I_D = f(V_GS) ; conditions: V_DS = 25 V; parameter T_j
gfs / S
20
Tj / C = 25
150
10
9830-30
0
0
10
20
30
40
50
60
ID / A
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D); conditions: V_DS = 25 V
a
2
SOT223 30V Trench Normalised RDS(ON) = f(Tj)
1.5
1
0.5
0
-50
0
50
100
150
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j); I_D = 3.2 A; V_GS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
January 1998
4
Rev 1.300