PHT6N03LT Datasheet, PDF (3/6 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W_DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I_D = 5.9 A; V_DD ≤ 15 V;
V_GS = 10 V; R_GS = 50 Ω; T_amb = 25 ˚C
Product specification
PHT6N03LT
MIN.
-
MAX.
60
UNIT
mJ
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tamb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_amb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Ambient temperature, Tamb (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_amb); conditions: V_GS ≥ 5 V
ID / A
100
10
RDS(ON) ^{= VDS / ID}
1
DC
0.1
7830-30
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.01
0.1
1
10
100
1000
VDS / V
Fig.3. Safe operating area. T_amb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth j-amb / (K/W)
1E+02
D=
0.5
BUKX83
0.2
1E+01
0.1
0.05
0.02
1E+00
P
D
t_p
D = ^tp
T
1E-01
0
1E-02
1E-07
1E-05
1E-03 1E-01
t/s
t
T
1E+01 1E+03
Fig.4. Transient thermal impedance.
Z_{th j-amb} = f(t); parameter D = t_p/T
January 1998
3
Rev 1.300