PHT6N03LT Datasheet, PDF (1/6 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT6N03LT
FEATURES
SYMBOL
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Surface mounting package
d
g
s
QUICK REFERENCE DATA
V_DSS = 30 V
I_D = 5.9 A
R_DS(ON) ≤ 30 mΩ (V_GS = 5 V)
R_DS(ON) ≤ 28 mΩ (V_GS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor
using
’trench’
technology. The device has very
low on-state resistance. It is
intended for use in dc to dc
converters and general purpose
switching applications.
The PHT6N03LT is supplied in the
SOT223 surface mounting
package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
SOT223
4
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 150˚C
T_j = 25 ˚C to 150˚C; R_GS = 20 kΩ
T_amb = 25 ˚C; V_GS = 10 V
T_amb = 100 ˚C; V_GS = 10 V
T_amb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
± 13
5.9
4.1
23.6
1.8
150
UNIT
V
V
V
A
A
A
W
˚C
ESD LIMITING VALUE
SYMBOL PARAMETER
V_C
Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
Human body model (100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL PARAMETER
R_{th j-sp}
R_{th j-a}
Thermal resistance junction
to solder point
Thermal resistance junction
to ambient
CONDITIONS
mounted on any pcb
mounted on test pcb of fig:17
MIN. TYP. MAX. UNIT
-
- 15 K/W
- 70 - K/W
January 1998
1
Rev 1.300