PHP21N06LT Datasheet, PDF (5/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET

Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP21N06LT, PHB21N06LT
PHD21N06LT
1.0E-01 ^{Drain current, ID (A)}
1.0E-02
1.0E-03
1.0E-04
1.0E-05
minimum
typical
maximum
1.0E-06
0
0.5
1
1.5
2
2.5
3
Gate-source voltage, VGS (V)
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
Capacitances, Ciss, Coss, Crss (pF)
10000
1000
Ciss
Coss
100
Crss
10
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
Gate-source voltage, VGS (V)
15
14 ^{ID = 20A}
13 Tj = 25 C
12
11
10
VDD = 11 V
9
8
7
VDD = 44 V
6
5
4
3
2
1
0
0
2
4
6
8 10 12 14 16 18 20
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G)
Source-Drain Diode Current, IF (A)
30
VGS = 0 V
25
20
15
175 C
Tj = 25 C
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
Maximum Avalanche Current, IAS (A)
100
10
25 C
1
Tj prior to avalanche = 150 C
0.1
0.001
0.01
0.1
1
10
Avalanche time, tAV (ms)
Fig.15. Maximum permissible non-repetitive
avalanche current (I_AS) versus avalanche time (t_AV);
unclamped inductive load
August 1999
5
Rev 1.500