PHP21N06LT Datasheet, PDF (1/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET

Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP21N06LT, PHB21N06LT
PHD21N06LT
FEATURES
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
V_DSS = 55 V
I_D = 19 A
R_DS(ON) ≤ 75 mΩ (V_GS = 5 V)
R_DS(ON) ≤ 70 mΩ (V_GS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LT is supplied in the SOT404 (D²PAK) surface mounting package.
The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D²PAK)
PIN DESCRIPTION
tab
tab
1 gate
SOT428 (DPAK)
tab
2 drain ¹
3 source
tab drain
1 23
2
13
2
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
V_GSM
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 175˚C
T_j = 25 ˚C to 175˚C; R_GS = 20 kΩ
T_j ≤ 150˚C
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 15
± 20
19
13
76
56
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.500