PHP21N06LT Datasheet, PDF (4/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET

Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP21N06LT, PHB21N06LT
PHD21N06LT
35 ^{Drain Current, ID (A)}
Tj = 25 C
30
VGS = 10V
5V
25
20
3.4 V
15
10
5
0
0
3.2 V
3V
2.8 V
2.6 V
2.4 V
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS)
Drain-Source On Resistance, RDS(on) (Ohms)
0.3
2.6 V _2.8V
0.25
2.4 V
0.2
3V
Tj = 25 C
0.15
3.2 V
3.4 V
0.1
5V
0.05
0
0
VGS = 10V
5
10
15
20
25
30
35
Drain Current, ID (A)
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D)
Drain current, ID (A)
20
18 ^{VDS > ID X RDS(ON)}
16
14
12
10
8
6
4
175 C
2
Tj = 25 C
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
I_D = f(V_GS)
Transconductance, gfs (S)
15
14 ^{VDS > ID X RDS(ON)}
Tj = 25 C
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8 10 12 14
Drain current, ID (A)
175 C
16 18 20
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D)
Normalised On-state Resistance
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.9. Normalised drain-source on-state resistance.
R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j)
Threshold Voltage, VGS(TO) (V)
2.25
2
maximum
1.75
1.5
typical
1.25
1
minimum
0.75
0.5
0.25
0
-60 -40 -20
0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
August 1999
4
Rev 1.500