PHP21N06LT Datasheet, PDF (3/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET

Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP21N06LT, PHB21N06LT
PHD21N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T_j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
I_S
Continuous source current
(body diode)
I_SM
Pulsed source current (body
diode)
V_SD
Diode forward voltage
I_F = 20 A; V_GS = 0 V
t_rr
Reverse recovery time
I_F = 20 A; -dI_F/dt = 100 A/µs;
Q_rr
Reverse recovery charge V_GS = 0 V; V_R = 30 V
MIN. TYP. MAX. UNIT
-
- 19 A
-
- 76 A
- 1.2 1.5 V
- 43 - ns
- 94 - nC
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_mb)
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100 125 150 175
Mounting Base temperature, Tmb (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_mb); conditions: V_GS ≥ 5 V
100 ^{Peak Pulsed Drain Current, IDM (A)}
RDS(on) = VDS/ ID
10
D.C.
1
tp = 10 us
100 ms
100 us
1 ms
10 ms
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
10 ^{Transient thermal impedance, Zth j-mb (K/W)}
D = 0.5
1 0.2
0.1
0.05
0.02
0.1
single pulse
PD
tp ^{D = tp/T}
0.01
1E-06
1E-05
T
1E-04 1E-03 1E-02
Pulse width, tp (s)
1E-01
1E+00
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
August 1999
3
Rev 1.500