PHN203 Datasheet, PDF (5/7 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

Philips Semiconductors
Dual N-channel enhancement mode
TrenchMOS^TM transistor
Product specification
PHN203
1E-01
Sub-Threshold Conduction
1E-02
1E-03
min
typ max
1E-04
1E-05
1E-06
0
1
2
3
4
5
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C
Capacitances, Ciss, Coss, Crss (pF)
10000
PHN203
1000
Ciss
Coss
100
0.1
Crss
1
10
100
Drain-Source Voltage, VDS (V)
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
Source-Drain Diode Current, IF (A)
10
9 ^{VGS = 0 V}
PHN203
8
7
6
5
4
150 C
Tj = 25 C
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Drain-Source Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
Non-repetitive Avalanche current, IAS (A)
10
PHN203
25 C
VDS
tp
ID
Tj prior to avalanche =125 C
1
1E-06
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.15. Maximum permissible non-repetitive
avalanche current (I_AS) versus avalanche time (t_p);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14 ID = 4A
13
12
Tj = 25 C
11 VDD = 20 V
10
9
8
7
6
5
4
3
2
1
0
0
5
10
15
20
Gate charge, QG (nC)
PHN203
25
30
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G)
January 1999
5
Rev 1.000