PHN203 Datasheet, PDF (1/7 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

Philips Semiconductors
Dual N-channel enhancement mode
TrenchMOS^TM transistor
Product specification
PHN203
FEATURES
• Dual device
• Low threshold voltage
• Fast switching
• Logic level compatible
• Surface mount package
SYMBOL
d1 d1 d2 d2
s1 g1 s2 g2
QUICK REFERENCE DATA
V_DS = 25 V
I_D = 6.3 A
R_DS(ON) ≤ 30 mΩ (V_GS = 10 V)
R_DS(ON) ≤ 55 mΩ (V_GS = 4.5 V)
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope using ’trench’
technology. The device has very
low on-state resistance. It is
intended for use in dc to dc
converters and general purpose
switching applications.
The PHN203 is supplied in the
SOT96-1 (SO8) surface mounting
package.
PINNING
PIN
DESCRIPTION
1 source 1
2 gate 1
3 source 2
4 gate 2
5,6 drain 2
7,8 drain 1
SOT96-1
876 5
pin 1 index
123 4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DS
V_DGR
V_GS
I_D
I_D
I_DM
P_tot
T_stg, T_j
Repetitive peak drain-source
voltage
Continuous drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current per MOSFET¹
Drain current per MOSFET (both
MOSFETs conducting)¹
Drain current per MOSFET (pulse
peak value)
Total power dissipation (either or
both MOSFETs conducting)¹
Storage & operating temperature
T_j = 25 ˚C to 150˚C
R_GS = 20 kΩ
T_a = 25 ˚C
T_a = 70 ˚C
T_a = 25 ˚C
T_a = 70 ˚C
T_a = 25 ˚C
T_a = 25 ˚C
T_a = 70 ˚C
MIN.
-
-
-
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
25
± 20
6.3
5
4.4
3.5
25
2
1.3
150
UNIT
V
V
V
V
A
A
A
A
A
W
W
˚C
1 Surface mounted on FR4 board, t ≤ 10 sec
January 1999
1
Rev 1.000