PHN203 Datasheet, PDF (4/7 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

Philips Semiconductors
Dual N-channel enhancement mode
TrenchMOS^TM transistor
Product specification
PHN203
Drain Current, ID (A)
10
9 ^10V
VGS = 5 V
8
PHN203
Tj = 25 C
3.6 V
7
3.4 V
6
5
4
3.2 V
3
3V
2
2.8 V
1
2.6 V
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
Drain-Source On Resistance, RDS(on) (Ohms) PHN203
0.5
2.6V _{2.8V 3 V}
3.2 V
Tj = 25 C
0.4
3.4V
0.3
3.6V
0.2
0.1
10V VGS =5 V
0
0 1 2 3 4 5 6 7 8 9 10
Drain Current, ID (A)
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
Drain current, ID (A)
10
9 ^{VDS > ID X RDS(ON)}
8
7
6
5
4
150 C
Tj = 25 C
3
2
1
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Gate-source voltage, VGS (V)
PHN203
4.5 5
Fig.7. Typical transfer characteristics.
I_D = f(V_GS)
Transconductance, gfs (S)
14
13 VDS > ID X RDS(ON)
12
11
10
9
8
7
6
5
4
3
2
1
0
01234567
Drain current, ID (A)
PHN203
Tj = 25 C
150 C
8 9 10
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D)
a
2
SOT223 30V Trench Normalised RDS(ON) = f(Tj)
1.5
1
0.5
0
-50
0
50
100
150
Tj / C
Fig.9. Normalised drain-source on-state resistance.
R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j)
VGS(TO) / V
4
3
max.
typ.
2
1
min.
0
-60 -40 -20 0
20 40 60 80 100 120 140
Tj / C
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
January 1999
4
Rev 1.000