74ABT853 Datasheet, PDF (5/7 Pages) NXP Semiconductors – 8-bit transceiver with 9-bit parity checker/ generator and flag latch 3-State

Philips Semiconductors
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
Product specification
74ABT853
AC CHARACTERISTICS
GND = 0V; t_R = t_F = 2.5ns; C_L = 50pF, R_L = 500Ω
SYMBOL
PARAMETER
t_PLH
Propagation delay
t_PHL
An to Bn or Bn to An
t_PLH
Propagation delay
t_PHL
An to PARITY
t_PLH
Propagation delay
t_PHL
OEA to PARITY
t_PLH
Propagation delay
CLEAR to ERROR
t_PLH
Propagation delay
t_PHL
ENABLE to ERROR
t_PLH
Propagation delay
t_PHL
Bn or PARITY to ERROR
t_PZH
Output enable time
t_PZL
OEA to An or OEB to Bn, PARITY
t_PHZ
Output disable time
t_PLZ
OEA to An or OEB to Bn, PARITY
WAVEFORMS
4
1, 4
1, 4
3
4
1, 4
2, 5
2, 5
LIMITS
T_amb = +25^oC
V_CC = +5.0V
Min
Typ
Max
T_amb = –40 to +85^oC
V_CC = +5.0V ±10%
Min
Max
UNIT
1.2
3.4
1.0
2.6
4.8
1.2
4.0
1.0
5.3
4.5
ns
2.1
7.4
2.5
7.4
9.5
9.7
2.1
2.5
11.2
11.0
ns
1.8
6.6
2.3
6.7
8.5
8.6
1.8
2.3
10.5
10.0
ns
1.0
3.6
5.5
1.0
6.2
ns
1.8
3.8
1.8
4.5
5.1
1.8
5.8
1.8
6.0
6.6
ns
2.0
3.0
7.9
9.0
10.1
11.5
2.0
3.0
11.7
12.8
ns
1.0
3.2
2.1
4.1
5.1
1.0
5.8
2.1
6.2
6.7
ns
3.1
5.1
3.2
5.6
7.3
3.1
7.2
3.2
7.9
8.1
ns
AC SETUP REQUIREMENTS
GND = 0V; t_R = t_F = 2.5ns; C_L = 50pF, R_L = 500Ω
SYMBOL
PARAMETER
t_s(H)
t_s(L)
t_h(H)
t_h(L)
t_s(H)
t_h(L)
t_w(L)
t_w(L)
Setup time, High or Low
Bn or PARITY to ENABLE
Hold time, High or Low
Bn or PARITY to ENABLE
Setup time, High
CLEAR to ENABLE
Hold time, Low
CLEAR to ENABLE
Pulse width, Low
CLEAR
Pulse width, Low
ENABLE
WAVEFORMS
6
6
6
6
3
6
T_amb = +25^oC
V_CC = +5.0V
MIN
TYP
8.5
6.5
8.5
3.6
0.0
–3.4
0.0
–6.3
2.0
–1.6
3.0
1.8
3.5
1.0
4.0
2.5
LIMITS
T_amb = –40 to +85^oC
V_CC = +5.0V ±10%
MIN
8.5
8.5
0.0
0.0
2.0
3.0
3.5
4.0
UNIT
ns
ns
ns
ns
ns
ns
1995 Sep 06
5