74ABT853 Datasheet, PDF (2/7 Pages) NXP Semiconductors – 8-bit transceiver with 9-bit parity checker/ generator and flag latch 3-State

Philips Semiconductors
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
Product specification
74ABT853
PIN DESCRIPTION
SYMBOL
A0 – A7
B0 – B7
OEA
OEB
PARITY
ERROR
CLEAR
ENABLE
GND
V_CC
PIN NUMBER
2, 3, 4, 5, 6, 7, 8, 9
23, 22, 21, 20, 19, 18, 17, 16
1
14
15
10
11
13
12
24
NAME AND FUNCTION
A port 3–State inputs/outputs
B port 3–State inputs/outputs
Enables the A outputs when Low
Enables the B outputs when Low
Parity output/input
Error output (open collector)
Clears the error flag register when Low
Enable input (active-Low)
Ground (0V)
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
OEB OEA
An
Σ OF HIGHS
Bn + PARITY
Σ OF HIGHS
An
Bn
PARITY
A data to B bus and generate odd parity output
B data to A bus and check for parity error¹
A bus and B bus disabled²
L
H
H
L
H
H
Odd
Even
(output)
X
(output)
X
X
(input) An
Bn (input)
Z
Z
L
H
(input)
Z
A data to B bus and generate inverted parity output
L
L
Odd
Even
(output)
(input) An
H
L
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
MODE
ENABLE
CLEAR
Pass
L
L
Sample
Clear
L
H
H
L
Bn + PARITY
Σ OF HIGHS
Odd
Even
Odd
Even
X
X
Store
H
H
X
H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
Z = High impedance ”off” state
INTERNAL NODE
POINT ”P”
H
L
H
L
X
X
X
OUTPUT
PRE–STATE
ERRORn–1
X
H
X
L
X
L
H
ERROR
OUTPUT
H
L
H
L
L
H
L
H
1995 Sep 06
2