PHT8N06LT Datasheet, PDF (4/9 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT8N06LT
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_sp)
ID%
120
110
100
90
Normalised Current Derating
80
70
60
50
40
30
20
10
0
0
20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_sp); conditions: V_GS ≥ 5 V
100
ID/A
RDS(ON) = VDS/ID
10
DC
1
tp =
1 us
10us
100 us
1 ms
10ms
100ms
0.1
1
10 _VDS/V
100
Fig.3. Safe operating area. T_sp = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
100 ^{Zth/ (K/W)}
10 _0.5
0.2
0.1
1 _0.05
0.02
0.1
P_D
tp
D
=
tp
T
T
t
0.01
1.0E-06
0.0001 _t/s 0.01
1
100
Fig.4. Transient thermal impedance.
Z_{th j-sp} = f(t); parameter D = t_p/T
Drain current, ID (A)
40
10
7
6
30
20
VGS = 5.0 V
4.6
4.0
3.6
3.2
10
3.0
2.4
2.6
0
0
2 _{Drain-s4ource voltag6e, VDS (V)} 8
10
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
115 ^RDS(ON)/mOhm
110
105
4.2
4
100
4.4
95
4.6
4.8
5
90
85
80
75
70
5
Fig.6.
10 _ID/A
15
20
25
Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
January 1998
4
Rev 1.100