PHT8N06LT Datasheet, PDF (1/9 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT8N06LT
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
DC-DC converters and general
purpose switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V_GS = 5 V
MAX.
55
7.5
1.8
150
80
PINNING - SOT223
PIN
DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
PIN CONFIGURATION
4
1
2
3
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_D
I_DM
P_tot
P_tot
T_stg, T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
-
R_GS = 20 kΩ
-
T_sp = 25 ˚C
On PCB in Fig.2
T_amb = 25 ˚C
On PCB in Fig.2
T_amb = 100 ˚C
T_sp = 25 ˚C
T_sp = 25 ˚C
On PCB in Fig.2
T_amb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
V_C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
13
7.5
3.5
2.2
40
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
W
W
˚C
MIN.
-
MAX.
2
UNIT
kV
January 1998
1
Rev 1.100