PHP42N03LT Datasheet, PDF (4/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP42N03LT, PHB42N03LT
ID, Drain current (Amps)
80 _{15 V}
5V
70 ^{10 V}
Tj = 25 C
PHP45N03LT
4.5 V
60
4V
50
40
3.5 V
30
20
3V
10
VGS = 2.5 V
0
0
2
4
6
8
10
VDS, Drain-Source voltage (Volts)
Fig.5. Typical output characteristics
I_D = f(V_DS); parameter V_GS
Drain-Source on resistance, RDS(on) (Ohms)
0.06
3V
3.5 V
4V
4.5 V
0.05
0.04
0.03
5V
0.02
10 V
0.01
VGS = 15 V
Tj = 25 C
0
0 10 20 30 40 50 60 70 80
PHP45N03LT ^{ID, Drain current (Amps)}
Fig.6. Typical on-state resistance
R_DS(ON) = f(I_D); parameter V_GS
50 ^{Drain current, ID (A)}
VDS = 25 V
40
PHP45N03LT
30
20
10
175 C
Tj = 25 C
0
0
1
2
3
4
5
6
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
I_D = f(V_GS)
30 ^{Transconductance, gfs (S)}
VDS = 25 V
25
PHP45N03LT
Tj = 25 C
20
175 C
15
10
5
0
0
10
20
30
40
50
Drain current, ID (A)
Fig.8. Typical transconductance
g_fs = f(I_D)
a
2
30V TrenchMOS
1.5
1
0.5
0
-100
-50
0
50
100
150
200
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j)
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
November 1998
4
Rev 1.400