PHP42N03LT Datasheet, PDF (3/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP42N03LT, PHB42N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T_j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
I_S
Continuous source current
(body diode)
I_SM
Pulsed source current (body
diode)
V_SD
Diode forward voltage
I_F = 25 A; V_GS = 0 V
I_F = 40 A; V_GS = 0 V
t_rr
Reverse recovery time
I_F = 40 A; -dI_F/dt = 100 A/µs;
Q_rr
Reverse recovery charge V_GS = -10 V; V_R = 25 V
MIN. TYP. MAX. UNIT
-
- 45 A
-
- 180 A
- 0.95 1.2 V
- 1.0 -
- 52 - ns
- 0.08 - µC
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_mb)
ID%
120
110
Normalised Current Derating
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_mb); conditions: V_GS ≥ 5 V
1000 ^{ID, Drain current (Amps)}
PHP42N03LT
100
RDS(ON) ^{= VDS/ID}
tp = 10us
100 us
1 ms
10
DC
10 ms
100 ms
Tmb = 25 C
1
1
10
100
VDS, Drain-source voltage (Volts)
Fig.3. Safe operating area
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth j-mb / (K/W)
10
D=
7528-30
1
0.5
0.2
0.1 ^0.1
0.05
0.02
P_D
tp
D=
tp
T
0
0.01
1E-07
1E-05
1E-03
t/s
T
t
1E-01
1E+01
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
November 1998
3
Rev 1.400