NPIC6C595_15 Datasheet, PDF (4/20 Pages) NXP Semiconductors – Power logic 8-bit shift register; open-drain outputs

NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
6. Pinning information
6.1 Pinning
V_CC 1
DS 2
Q0 3
Q1 4
Q2 5
Q3 6
MR 7
OE 8
NPIC6C595
16 GND
15 SHCP
14 Q7
13 Q6
12 Q5
11 Q4
10 STCP
9 Q7S
aaa-003482
Fig 7. Pin configuration SO16 and TSSOP16
terminal 1
index area
NPIC6C595
DS 2
Q0 3
Q1 4
Q2 5
Q3 6
MR 7
GND⁽¹⁾
15 SHCP
14 Q7
13 Q6
12 Q5
11 Q4
10 STCP
aaa-003483
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 8. Pin configuration DHVQFN16
6.2 Pin description
Table 2. Pin description
Symbol
V_CC
DS
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
MR
OE
Q7S
STCP
SHCP
GND
Pin
1
2
3, 4, 5, 6, 11, 12, 13, 14
7
8
9
10
15
16
Description
supply voltage
serial data input
parallel data output (open-drain)
master reset (active LOW)
output enable input (active LOW)
serial data output
storage register clock input
shift register clock input
ground (0 V)
NPIC6C595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 August 2012
© NXP B.V. 2012. All rights reserved.
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