BUK130-50DL Datasheet, PDF (4/6 Pages) NXP Semiconductors – Logic level TOPFET SMD version of BUK119-50DL

Philips Semiconductors
Logic level TOPFET
SMD version of BUK119-50DL
Product specification
BUK130-50DL
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40˚C ≤ T_mb ≤ 150˚C; typicals are for T_mb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
V_IS(TO)
I_IS
I_ISL
V_ISR
t_lr
V_(CL)IS
R_IG
Input threshold voltage
Input supply current
Input supply current
Protection reset voltage¹
Latch reset time
Input clamping voltage
Input series resistance²
to gate of power MOSFET
V_DS = 5 V; I_D = 1 mA
0.6
T_mb = 25˚C 1.1
normal operation;
V_IS = 5 V
100
V_IS = 4 V
80
protection latched;
V_IS = 5 V
200
V_IS = 3 V
130
reset time t_r ≥ 100 µs
1.5
V_IS1 = 5 V, V_IS2 < 1 V
10
I_I = 1.5 mA
5.5
T_mb = 25˚C
-
TYP.
-
1.6
220
195
400
250
2
40
-
33
MAX. UNIT
2.4 V
2.1 V
400 µA
330 µA
650 µA
430 µA
2.9 V
100 µs
8.5 V
-
kΩ
SWITCHING CHARACTERISTICS
T_mb = 25˚C; V_DD = 13 V; resistive load R_L = 4 Ω. Refer to waveform figure and test circuit.
SYMBOL PARAMETER
CONDITIONS
MIN.
t_{d on}
Turn-on delay time
V_IS = 5 V
-
t_r
Rise time
-
t_{d off}
Turn-off delay time
V_IS = 0 V
-
t_f
Fall time
-
TYP.
25
50
60
50
MAX. UNIT
50 µs
100 µs
120 µs
100 µs
1 The input voltage below which the overload protection circuits will be reset.
2 Not directly measureable from device terminals.
May 2001
4
Rev 1.900