83C754 Datasheet, PDF (4/26 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

Philips Semiconductors
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
83C754/87C754
PIN DESCRIPTION
MNEMONIC
DIP
TYPE
PIN NO.
NAME AND FUNCTION
V_SS
V_CC
P1.0–P1.2
P3.0–P3.7
8
I Circuit Ground Potential.
22
I Supply voltage during normal, idle, and power-down operation.
21, 23, 24 I/O Port 1: Port 1 is a 3-bit bidirectional I/O port with internal pull-ups on P1.0 and P1.1. Port 1 pins that
have 1s written to them can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups (P1.0, P1.1). (See DC Electrical Characteristics: I_IL).
Port 1 also serves the special function features listed below (Note: P1.0 does not have the strong
pullup that is on for 2 oscillator periods.):
24
I INT0 (P1.0): External interrupt 0.
23
O CEX (P1.1): PCA clock output.
21
I V_PP (P1.2): Programming voltage input (open drain).
1–4,
25–28
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I_IL). Port 3 also functions as the data input for the EPROM memory location to be
programmed (or verified). (Note: P3.5 does not have the strong pullup that is on for 2 oscillator
periods.)
Port 3 also serves the special function as listed below:
3
I ECI (P3.6): External PCA clock input.
1
I RxD/T0 (P3.4): Serial port receiver data input.
Timer 0 external clock input.
4
I INT1: External interrupt 1.
2
I TxD/T1 (P3.5): Serial port transmitter data.
Timer 1 external clock input.
RST
5
I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. After
the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the
programming state allowing programming address, data and V_PP to be applied for programming or
verification purposes. The RESET serial sequence must be synchronized with the X1 input. (Note: The
83/87C754 does not have an internal reset resistor.)
X1
7
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
AV_CC ¹
AV_SS ¹
ZIN
6
O Crystal 2: Output from the inverting oscillator amplifier.
14
I Analog supply voltage and reference input.
13
I Analog supply and reference ground.
9
I ZIN: Input to analog multiplexer.
YIN
10
I YIN: Input to analog multiplexer.
XIN
11
I XIN: Input to analog multiplexer.
XYZRAMP
12
O XYZRAMP: Provides a low impedance pulldown to V_SS under S/W control.
DECOUPLE
15
O Decouple: Output from regulated supply for connection of decoupling capacitors.
VREG
16
O VREG: Provides regulated analog supply output.
XYDACBIAS
17
O XYDACBIAS: Provides source voltage for bias of external circuitry.
– Input which specifies verify mode (output enable) or the program mode.
/PGM = 1 output enabled (verify mode).
/PGM = 0 program mode.
XYSOURCE
18
O XYSOURCE: Provides source voltage from regulated analog supply.
ZDAC
19
O ZDAC: Switchable outp from the internal DAC.
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
XYDAC
20
O XYDAC: Non-switchable output from the internal DAC.
NOTE:
1. AV_SS (reference ground) must be connected to 0V (ground). AV_CC (reference input) cannot differ from V_CC by more than ±0.2V, and must be
in the range 4.5V to 5.5V.
1998 Apr 23
4