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| 83C754 Datasheet, PDF (22/26 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference | |||
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Philips Semiconductors
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
EPROM PROGRAMMING AND VERIFICATION
Tamb = 21°C to +27°C, VCC = 5V ±10%, VSS = 0V
SYMBOL
PARAMETER
MIN
1/tCLCL
tAVGL1
Oscillator/clock frequency
Address setup to PGM low
1.2
10µs + 24tCLCL
tGHAX
Address hold after PGM high
48tCLCL
tDVGL
Data setup to PGM low
38tCLCL
tDVGL
Data setup to PGM low
38tCLCL
tGHDX
Data hold after PGM high
36tCLCL
tSHGL
VPP setup to PGM low
10
tGHSL
VPP hold after PGM
10
tGLGH
PGM width
90
tAVQV2
VPP low (VCC) to data valid
tGHGL
PGM high to PGM low
10
tSYNL
P0.0 (sync pulse) low
4tCLCL
tSYNH
P0.0 (sync pulse) high
8tCLCL
tMASEL
ASEL high time
13tCLCL
tMAHLD
Address hold time
2tCLCL
tHASET
Address setup to ASEL
13tCLCL
tADSTA
Low address to address stable
13tCLCL
NOTES:
1. Address should be valid at least 24tCLCL before the rising edge of VPP.
2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.
A0âA10
ADDRESS STROBE
PROGRAMMING
PULSES
VPP/VIH VOLTAGE
SOURCE
CLK SOURCE
RESET
CONTROL
LOGIC
87C754
A0âA10
ZDAC/ASEL
VCC
VSS
XYDACBIAS/PGM
P1.2/VPP
X1
P3.0âP3.7
RST
Figure 20. Programming Configuration
Preliminary specification
83C754/87C754
MAX
16
UNIT
MHz
µs
µs
110
µs
48tCLCL
µs
+5V
DATA BUS
SU00667A
1998 Apr 23
22
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