83C754 Datasheet, PDF (12/26 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

Philips Semiconductors
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
83C754/87C754
CMOD Address = OD9H
Reset Value = 00XX X000B
Bit Addressable
CIDL WDTE
–
–
–
CPS1 CPS0
ECF
Bit:
7
6
5
4
3
2
1
0
Symbol Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module. WDTE = 1 enables it.
–
Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1 CPS0 Selected PCA Input**
0
0
0
1
1
0
0
Internal clock, f_OSC ÷ 12
1
Internal clock, f_OSC ÷ 4
2
Timer 0 overflow
1
1
3
External clock at ECI/P3.1 pin (max. rate = f_OSC ÷ 8)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** f_OSC = oscillator frequency
SU00675A
Figure 8. CMOD: PCA Counter Mode Register
CCON Address = OD8H
Reset Value = 00X0 0000B
Symbol
CF
CR
–
CCF
Bit Addressable
CF
CR
––
CCF
––
––
––
––
Bit:
7
6
5
4
3
2
1
0
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
PCA Module interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00676A
Figure 9. CCON: PCA Counter Control Register
1998 Apr 23
12