XA-G39 Datasheet, PDF (33/42 Pages) NXP Semiconductors – XA 16-bit microcontroller family XA 16-bit microcontroller 32K FLASH/1K RAM, watchdog, 2 UARTs

Philips Semiconductors
XA 16-bit microcontroller family
32K Flash/1K RAM, watchdog, 2 UARTs
Preliminary data
XA-G39
AC ELECTRICAL CHARACTERISTICS (5 V)
V_DD = 4.5 V to 5.5 V; T_amb = 0 to +70 °C for commercial; V_DD = 4.75 V to 5.25 V, –40 °C to +85 °C for industrial.
SYMBOL FIGURE
PARAMETER
VARIABLE CLOCK
MIN
MAX
External Clock
f_C
t_C
26
t_CHCX
26
t_CLCX
26
t_CLCH
26
t_CHCL
26
Address Cycle
Oscillator frequency
Clock period and CPU timing cycle
Clock high time
Clock low time
Clock rise time
Clock fall time
0
30
1/f_C
t_C * 0.5 ⁷
t_C * 0.4 ⁷
5
5
t_CRAR
25
t_LHLL
20
t_AVLL
20
t_LLAX
20
Code Read Cycle
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
Address valid to ALE de-asserted (set-up)
Address hold after ALE de-asserted
5
46
(V1 * t_C) – 6
(V1 * t_C) – 14
(t_C/2) – 10
t_PLPH
20
t_LLPL
20
t_AVIVA
20
t_AVIVB
21
t_PLIV
20
t_PXIX
20
t_PXIZ
20
t_IXUA
20
Data Read Cycle
PSEN pulse width
ALE de-asserted to PSEN asserted
Address valid to instruction valid, ALE cycle (access time)
Address valid to instruction valid, non-ALE cycle (access time)
PSEN asserted to instruction valid (enable time)
Instruction hold after PSEN de-asserted
Bus 3-State after PSEN de-asserted (disable time)
Hold time of unlatched part of address after instruction latched
(V2 * t_C) – 10
(t_C/2) – 7
0
0
(V3 * t_C) – 36
(V4 * t_C) – 29
(V2 * t_C) – 29
t_C – 8
t_RLRH
22
t_LLRL
22
t_AVDVA
22
t_AVDVB
23
t_RLDV
22
t_RHDX
22
t_RHDZ
22
t_DXUA
22
Data Write Cycle
RD pulse width
ALE de-asserted to RD asserted
Address valid to data input valid, ALE cycle (access time)
Address valid to data input valid, non-ALE cycle (access time)
RD low to valid data in, enable time
Data hold time after RD de-asserted
Bus 3-State after RD de-asserted (disable time)
Hold time of unlatched part of address after data latched
(V7 * t_C) – 10
(t_C/2) – 7
0
0
(V6 * t_C) – 36
(V5 * t_C) – 29
(V7 * t_C) – 29
t_C – 8
t_WLWH
24
t_LLWL
24
t_QVWX
24
t_WHQX
24
t_AVWL
24
t_UAWH
24
Wait Input
WR pulse width
ALE falling edge to WR asserted
Data valid before WR asserted (data setup time)
Data hold time after WR de-asserted (Note 6)
Address valid to WR asserted (address setup time) (Note 5)
Hold time of unlatched part of address after WR is de-asserted
(V8 * t_C) – 10
(V12 * t_C) – 10
(V13 * t_C) – 22
(V11 * t_C) – 7
(V9 * t_C) – 22
(V11 * t_C) – 7
t_WTH
25
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
(V10 * t_C) – 30
t_WTL
25
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
(V10 * t_C) – 5
NOTES:
1. Load capacitance for all outputs = 80pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL).
Refer to the XA User Guide for details of the bus timing settings.
V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register.
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2002 Mar 13
33