TDA6402 Datasheet, PDF (3/40 Pages) NXP Semiconductors – 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners

Philips Semiconductors
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Product specification
TDA6402; TDA6402A;
TDA6403; TDA6403A
The device can be controlled according to the I²C-bus
format or 3-wire bus format depending on the voltage
applied to pin SW (see Table 2). In the 3-wire bus mode
(SW = HIGH), pin LOCK/ADC is the LOCK output.
The LOCK output is LOW when the PLL loop is locked.
In the I²C-bus mode (SW = LOW), the lock detector bit FL
is set to logic 1 when the loop is locked and is read on the
SDA line (Status Byte; SB) during a READ operation in
I²C-bus mode only. The Analog-to-Digital Converter
(ADC) input is available on pin LOCK/ADC for digital AFC
control in the I²C-bus mode only. The ADC code is read
during a READ operation on the I²C-bus (see Table 11).
In test mode, pin LOCK/ADC is used as a TEST output for
f_REF and ¹â„₂f_DIV, in both I²C-bus mode and 3-wire bus mode
(see Table 7).
When the automatic charge pump current switch mode is
activated and when the loop is phase-locked, the charge
pump current value is automatically switched to LOW. This
action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag
during a READ operation on the I²C-bus (see Table 9).
I²C-bus mode (SW = GND)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four ports, set the charge pump current and set the
reference divider ratio. The device has four independent
I²C-bus addresses which can be selected by applying a
specific voltage on input CE (see Table 6).
3-wire bus mode (SW = OPEN or VCC)
Data is transmitted to the devices during a HIGH-level on
input CE (enable line). The device is compatible with 18-bit
and 19-bit data formats, as shown in Figs 4 and 5. The first
four bits are used to program the PNP ports and the
remaining bits control the programmable divider. A 27-bit
data format may also be used to set the charge pump
current, the reference divider ratio and for test purposes
(see Fig.6).
It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits.
Table 1 Data word length for 3-wire bus
TYPE NUMBER
TDA6402; TDA6402A; TDA6403; TDA6403A
TDA6402; TDA6402A; TDA6403; TDA6403A
TDA6402; TDA6402A; TDA6403; TDA6403A
DATA WORD REFERENCE DIVIDER⁽¹⁾ FREQUENCY STEP
18-bit
512
62.50 kHz
19-bit
1 024
31.25 kHz
27-bit
programmable
programmable
Note
1. The selection of the reference divider is given by an automatic identification of the data word length. When the 27-bit
format is used, the reference divider is controlled by RSA and RSB bits (see Table 8). More details are given in
Chapter “PLL functional description”, Section “3-wire bus mode (SW = OPEN or V_CC)”.
2000 Jan 24
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