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TDA6402 Datasheet, PDF (17/40 Pages) NXP Semiconductors – 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Philips Semiconductors
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Product specification
TDA6402; TDA6402A;
TDA6403; TDA6403A
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
CE/AS INPUT (CHIP ENABLE/ADDRESS SELECTION)
VCE/ASL LOW-level input voltage
0
VCE/ASH HIGH-level input voltage
3
ICE/ASH HIGH-level input current
VCE/AS = 5.5 V
−
ICE/ASL LOW-level input current
VCE/AS = 0 V
−10
CL AND DA INPUTS
VCL/DAL LOW-level input voltage
0
VCL/DAH HIGH-level input voltage
3
ICL/DAH HIGH-level input current
VBUS = 5.5 V; VCC = 0 V
−
VBUS = 5.5 V; VCC = 5.5 V
−
ICL/DAL
LOW-level input current
VBUS = 1.5 V; VCC = 0 V
−
VBUS = 0 V; VCC = 5.5 V
−10
DA OUTPUT (I2C-BUS MODE)
IDAH
leakage current
VDA
output voltage
VDA = 5.5 V
−
IDA = 3 mA (sink current)
−
CLOCK FREQUENCY
fclk
clock frequency
−
CHARGE PUMP OUTPUT CP
ICPH
HIGH-level input current
CP = 1
−
(absolute value)
ICPL
LOW-level input current
CP = 0
−
(absolute value)
VCP
output voltage
PLL is locked; Tamb = 25 °C
−
ICPleak
off-state leakage current
T2 = 0; T1 = 1
−15
TUNING VOLTAGE OUTPUT VT
IVTOFF
leakage current when
switched off
OS = 1; tuning supply = 33 V
−
VVT
output voltage when the loop OS = 0; T2 = 0; T1 = 0; T0 = 1;
0.2
is closed
RLOAD = 22 kΩ; tuning supply = 33 V
3-WIRE BUS TIMING
tHIGH
clock HIGH time
see Fig.7
2
tSU;DA
data set-up time
see Fig.7
2
tHD;DA
data hold time
see Fig.7
2
tSU;ENCL enable to clock set-up time
see Fig.7
10
tHD;ENDA enable to data hold time
see Fig.7
2
tEN
enable time between two
see Fig.8
10
transmissions
tHD;ENCL enable to clock active edge see Fig.8
6
hold time
−
1.5
V
−
5.5
V
−
10
µA
−
−
µA
−
1.5
V
−
5.5
V
−
10
µA
−
10
µA
−
10
µA
−
−
µA
−
10
µA
−
0.4
V
100
150 kHz
280 −
µA
60
−
µA
1.95 −
V
−0.5 +15 nA
−
10
µA
−
32.7 V
−
−
µs
−
−
µs
−
−
µs
−
−
µs
−
−
µs
−
−
µs
−
−
µs
2000 Jan 24
17