GTL2002 Datasheet, PDF (3/14 Pages) NXP Semiconductors – 2-bit bi-directional low voltage translator

Philips Semiconductors
2-bit bi-directional low voltage translator
Product data sheet
GTL2002
PIN CONFIGURATION
GND 1
S_REF ²
S₁ 3
S₂ 4
8 G_REF
7 _DREF
6 D₁
5 D2
SA00640
Figure 1. SO8 and TSSOP8 pinning
S_REF 1
S₁ ²
S₂ 3
GND 4
8 G_REF
7 _DREF
6 D₁
5 D2
SA00658
Figure 2. VSSOP8 pinning
PIN DESCRIPTION
PIN NUMBER
SO8 and
TSSOP8
VSSOP8
SYMBOL
NAME AND FUNCTION
1
4
GND Ground (0 V)
2
1
S_REF Source of reference transistor
3, 4
2, 3
S_n
Port S₁ and Port S₂
5, 6
5, 6
D_n
Port D₁ and Port D₂
7
7
D_REF Drain of reference transistor
8
8
G_REF Gate of reference transistor
FUNCTION TABLE
HIGH-to-LOW translation assuming Dn is at the higher voltage level
G_REF
H
D_REF
H
S_REF
0V
In-Dn
X
Out-Sn
X
Transistor
Off
H
H
V_TT
H
V_TT1
On
H
H
V_TT
L
L²
On
L
L
0 – V_TT
X
X
Off
H = HIGH voltage level
L = LOW voltage level
X = Don’t Care
NOTES:
1. Sn is not pulled up or pulled down.
2. Sn follows the Dn input LOW.
3. G_REF should be at least 1.5 V higher than S_REF for best
translator operation.
4. V_TT is equal to the S_REF voltage.
FUNCTION TABLE
LOW-to-HIGH translation assuming Dn is at the higher voltage level
G_REF
H
D_REF
H
S_REF
0V
In-Sn
X
Out-Dn Transistor
X
Off
H
H
V_TT
V_TT
H
H
V_TT
L
L
L
0 – V_TT
X
H = HIGH voltage level
L = LOW voltage level
X = Don’t Care
H¹
nearly off
L²
On
X
Off
NOTES:
1. Dn is pulled up to V_CC through an external resistor.
2. Dn follows the Sn input LOW.
3. G_REF should be at least 1.5 V higher than S_REF for best
translator operation.
4. V_TT is equal to the S_REF voltage.
CLAMP SCHEMATIC
D_REF
G_REF
D1
D2
S_REF
S1
S2
SA00645
Figure 3. Clamp schematic
2004 Sep 29
3