GTL2002 Datasheet, PDF (2/14 Pages) NXP Semiconductors – 2-bit bi-directional low voltage translator

Philips Semiconductors
2-bit bi-directional low voltage translator
Product data sheet
GTL2002
FEATURES
• 2-bit bi-directional low voltage translator
• Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL,
GTL+, LVTTL/TTL and 5 V CMOS levels
• Provides bi-directional voltage translation with no direction pin
• Low 6.5 Ω RDS_ON resistance between input and output pins
(Sn/Dn)
• Supports hot insertion
• No power supply required - Will not latch up
• 5 V tolerant inputs
• Low stand-by current
• Flow-through pinout for ease of printed circuit board trace routing
• ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V per JESD22-C101
• Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8
APPLICATIONS
• Any application that requires bi-directional or unidirectional
voltage level translation from any voltage between 1.0 V and 5.0 V
to any voltage between 1.0 V and 5.0 V
• The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V)
processor I²C port translation to the normal 3.3 V or 5.0 V I²C-bus
signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.
DESCRIPTION
The Gunning Transceiver Logic — Transceiver Voltage Clamps
(GTL–TVC) provide high-speed voltage translation with low
ON-state resistance and minimal propagation delay. The GTL2002
provides 2 NMOS pass transistors (Sn and Dn) with a common gate
(G_REF) and a reference transistor (S_REF and D_REF). The device
allows bi-directional voltage translations between 1.0 V and 5.0 V
without use of a direction pin.
When the Sn or Dn port is LOW the clamp is in the ON-state and a
low resistance connection exists between the Sn and Dn ports.
Assuming the higher voltage is on the Dn port, when the Dn port is
high, the voltage on the Sn port is limited to the voltage set by the
reference transistor (S_REF). When the Sn port is high, the Dn port is
pulled to V_CC by the pull up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by
the user, without the need for directional control.
All transistors have the same electrical characteristics and there is
minimal deviation from one output to another in voltage or
propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical,
S_REF and D_REF can be located on any of the other two matched
Sn/Dn transistors, allowing for easier board layout. The translator’s
transistors provides excellent ESD protection to lower voltage
devices and at the same time protect less ESD resistant devices.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
8-Pin Plastic SO
–40 °C to +85 °C
GTL2002D
GTL2002
8-Pin Plastic TSSOP (MSOP)
–40 °C to +85 °C
GTL2002DP
2002
8-Pin Plastic VSSOP
–40 °C to +85 °C
GTL2002DC
2002
Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.
DWG NUMBER
SOT96–1
SOT505–1
SOT765–1
2004 Sep 29
2