PR31100 Datasheet, PDF (22/26 Pages) NXP Semiconductors – Highly integrated embedded processor

Philips Semiconductors
Highly integrated embedded processor
Preliminary specification
MIPS
PR31100
VIDEO
T_amb = 0 to +70°C, V_DD = 3.3 ± 0.3V, External Capacitance = 40pF
ITEM
PARAMETER
RISING/FALLING
LIMITS
MIN
MAX
1
LOAD Pulse width
–
100
1600
2
Delay LOAD Falling to FRAME
–
100
3200
3
Delay LOAD Falling to DF
–
100
3200
4
Delay LOAD Falling to CP
–
100
3200
5
Delay CP Rising to VDAT[3:0]
–
–
3
6
VDAT to CP Rising Setup
–
15
25
7
VDAT to CP Rising Hold
–
15
25
NOTE:
Values shown assume a 40MHz clock for the CPU, MIN and MAX values are programmable using Video Control Registers.
VIDEO TIMING DIAGRAMS
2
FRAME
UNIT
ns
ns
ns
ns
ns
ns
ns
DF
3
LOAD
CP
1
4
VDAT[3:0]
5
Figure 16. Video Timing, 4 Bit Non-Split LCD
CP
VDAT[3:0]
6
7
Figure 17. Video Data Timing, 4 Bit Split LCD and 8 Bit Non-Split LCD
1996 Aug 07
22