74HC595 Datasheet, PDF (2/28 Pages) NXP Semiconductors – 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

Philips Semiconductors
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
Product specification
74HC595; 74HCT595
FEATURES
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100 MHz (typical) shift out frequency
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register.
DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT595 is an 8-stage serial shift register with a
storage register and 3-state outputs. The shift register and
storage register have separate clocks.
Data is shifted on the positive-going transitions of the
SH_CP input. The data in each register is transferred to
the storage register on a positive-going transition of the
ST_CP input. If both clocks are connected together, the
shift register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided
with asynchronous reset (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state
bus driver outputs. Data in the storage register appears at
the output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
74HC 74HCT
UNIT
t_PHL/t_PLH propagation delay
SH_CP to Q7’
C_L = 50 pF; V_CC = 4.5 V
19
25
ns
SH_CP to Qn
20
24
ns
MR to Q7’
100
52
ns
f_max
maximum clock frequency SH_CP and ST_CP
C_I
input capacitance
C_PD
power dissipation capacitance per package
notes 1 and 2
100
57
MHz
3.5
3.5
pF
115
130
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + Σ(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts;
N = total load switching outputs;
Σ(C_L × V_CC2 × f_o) = sum of the outputs.
2. For 74HC595 the condition is V_I = GND to V_CC.
For 74HCT595 the condition is V_I = GND to V_CC − 1.5 V.
2003 Jun 25
2