74HC595 Datasheet, PDF (17/28 Pages) NXP Semiconductors – 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

Philips Semiconductors
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
Product specification
74HC595; 74HCT595
Family 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF.
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS V_CC (V)
MIN.
T_amb = 25 °C
t_PHL/t_PLH
propagation delay
SH_CP to Q7’
see Fig.7
4.5
−
propagation delay
ST_CP to Qn
see Fig.8
4.5
−
t_PHL
propagation delay
see Fig.10
4.5
−
MR to Q7’
t_PZH/t_PZL
3-state output enable time see Fig.11
OE to Qn
4.5
−
t_PHZ/t_PLZ
3-state output disable time see Fig.11
OE to Qn
4.5
−
t_W
shift clock pulse width
see Fig.7
4.5
16
HIGH or LOW
storage clock pulse width see Fig.8
HIGH or LOW
4.5
16
master reset pulse width see Fig.10
LOW
4.5
20
t_su
set-up time DS to SH_CP see Fig.9
4.5
16
set-up time
see Fig.8
4.5
16
SH_CP to ST_CP
t_h
hold time DS to SH_CP see Fig.9
4.5
+3
t_rem
removal time
MR to SH_CP
see Fig.10
4.5
+10
f_max
maximum clock
see Figs 7 and 8 4.5
30
pulse frequency
SH_CP or ST_CP
T_amb = −40 to +85 °C
t_PHL/t_PLH
propagation delay
SH_CP to Q7’
see Fig.7
propagation delay
ST_CP to Qn
see Fig.8
t_PHL
propagation delay
see Fig.10
MR to Q7’
t_PZH/t_PZL
3-state output enable time see Fig.11
OE to Qn
t_PHZ/t_PLZ
3-state output disable time see Fig.11
OE to Qn
4.5
−
4.5
−
4.5
−
4.5
−
4.5
−
TYP.
25
24
23
21
18
6
5
8
5
8
−2
−7
52
−
−
−
−
−
MAX.
42
40
40
35
30
−
−
−
−
−
−
−
−
53
50
50
44
38
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
2003 Jun 25
17