TDA8005A Datasheet, PDF (18/36 Pages) NXP Semiconductors – Low-power 3 V/5 V smart card coupler

Philips Semiconductors
Low-power (3 V/5 V) smart card coupler
Preliminary specification
TDA8005A
I/O buffer modes (see Fig.8)
The I/O buffer modes are:
• I/O buffer disabled
• I/O buffer in input, 20 kΩ pull-up resistor connected
between I/O and V_CC, I/O masked till 200 clock pulses
• I/O buffer in input, 20 kΩ pull-up resistor connected
between I/O and V_CC, I/O is sampled every 31 clock
pulses
• I/O buffer in output, 20 kΩ pull-up resistor connected
between I/O and V_CC
• I/O buffer in output, I/O is pulled LOW by the N transistor
of the buffer
• I/O buffer in output, I/O is pulled HIGH or LOW by the
P or N transistor.
Output ports extension
In the LQFP64 version, 6 auxiliary output ports may be
used for low frequency tasks (for example, keyboard
scanning). These ports are push-pull output types
(in accordance with use in software document).
Activation sequence
When the card is inactive, V_CC, CLK, RST and I/O are
LOW, with low impedance with respect to GND.
The step-up converter is stopped. The I/O is configured in
the reception mode with a high impedance path to the ISO
UART, subsequently no spurious pulse from the card
during power-up will be taken into account until I/O is
enabled. When conditions are fulfilled (supply voltage
present, card present, no hardware problems), the
microcontroller may initiate an activation sequence by
setting START LOW (t₀; see Fig.9):
1. The step-up converter is started (t₁)
2. LIS signal is disabled by internal signal ENLI, and V_CC
starts rising from 0 to 5 or 3 V (according to bit 4 of
UART configuration register) with a controlled rise time
of 0.1 V/µs typically (t₂)
3. I/O buffer is enabled (t₃)
4. Clock is sent to the card (t₄)
5. RST buffer is enabled (t₅).
In order to allow a precise count of clock pulses during
ATR, a defined time window (t₃; t₅) is opened where the
clock may be sent to the card by means of RSTIN
(port P04). Beyond this window, RSTIN has no more
action on clock, and only monitors the cards RST contact
(RST is the inverse of RSTIN).
The sequencer is clocked by f_INT/64 which leads to a time
interval T of 25 µs typical. Thus t₁ = 0 to ¹â„₆₄T,
t₂ = t₁ + ³â„₂T, t₃ = t₁ + 4T, t₄ = t₃ to t₅ and t₅ = t₁ + 7T.
Deactivation sequence
When the session is completed, the microcontroller sets
START HIGH. The circuit then executes an automatic
deactivation sequence (see Fig.10):
1. Card reset (RST falls LOW) at t₁₀
2. Clock is stopped at t₁₁
3. I/O becomes high impedance to the ISO UART (t₁₂)
4. V_CC falls to 0 V with typical 0.1 V/µs slew rate (t₁₃)
5. The step-up converter is stopped and CLK; RST, V_CC
and I/O become low impedance to GND (t₁₄)
6. t₁₀ < ¹â„₆₄T; t₁₁ = t₁₀ + ¹â„₂T; t₁₂ = t₁₀ + T; t₁₃ = t₁₀ + ³â„₂T;
t₁₄ = t₁₀ + 5T.
Protections
Main hardware fault conditions are monitored by the
circuit:
• Overcurrent on V_CC (in accordance with options as
specified in Table 3)
• Short circuits between V_CC and other contacts
• Card take-off during transaction.
When one of these problems is detected, the security logic
block pulls the interrupt line (port P10) OFF LOW, in order
to warn the microcontroller and initiates an automatic
deactivation of the contacts. When the deactivation has
been completed, the OFF line returns HIGH, except if the
problem was due to a card extraction in which case it
remains LOW until a card is inserted.
1998 Mar 20
18