TDA8360 Datasheet, PDF (17/36 Pages) NXP Semiconductors – Integrated PAL and PAL/NTSC TV processors

Philips Semiconductors
Integrated PAL and PAL/NTSC TV
processors
Objective specification
TDA8360; TDA8361; TDA8362
SYMBOL
PARAMETER
CONDITIONS
MIN.
Delay line and peaking circuit
Y DELAY LINE
t_d
delay time
note 7
−
B
bandwidth of internal delay line
note 7
8
PEAKING CONTROL; NOTE 28, SEE ALSO FIG.6 (PIN 14)
t_W
width of preshoot or overshoot
at 50% of pulse;
−
note 7
S_cth
peaking signal compression
−
threshold
I₁₄
input current when no video input
−
signal present
V_I
voltage level to switch off peaking
−
Horizontal and vertical synchronization circuits
SYNC VIDEO INPUT (TDA8361, TDA8362; PINS 13 AND 15)
V₁₃
sync pulse amplitude
referenced to pin 15; 50
note 3
SL
slicing level
note 29
−
VERTICAL SYNC
t_W
width of the vertical sync pulse
note 30
22
without sync instability
HORIZONTAL OSCILLATOR
f_fr
∆f_fr
∆f_osc/∆V_P
∆f_osc/∆T
∆f_{osc( max})
free running frequency
note 44
−
spread on free running frequency
−
frequency variation with respect to V_P = 8 V ±10%;
−
the supply voltage
note 7
frequency variation with temperature T_amb = 25 °C ±50 °C; −
note 7
maximum frequency deviation at the
−
start of the horizontal output
FIRST CONTROL LOOP; NOTE 31 (FILTER CONNECTED TO PIN 40)
f_HR
holding range PLL
−
f_CR
catching range PLL
note 7
±0.6
S/N
signal-to-noise ratio of the video input
−
signal at which the time constant is
switched
HYS
hysteresis at the switching point
−
TYP.
480
−
160
50
1
7
300
50
−
15 625
−
0.2
1
−
±0.9
±0.9
20
3
MAX.
−
−
−
−
−
−
−
−
−
−
±2
0.5
−
75
±1.2
−
−
−
UNIT
ns
MHz
ns
IRE
mA
V
mV
%
µs
Hz
%
%
Hz/K
%
kHz
kHz
dB
dB
March 1994
17