80C550 Datasheet, PDF (17/28 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
Product specification
80C550/83C550/87C550
AC ELECTRICAL CHARACTERISTICS
T_amb = 0°C to +70°C or –40°C to +85°C, V_CC = 5V ±10% (87C550), V_CC = 5V ±20% (80/83C550), V_SS = 0V^{1, 2}
16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX
1/t_CLCL
5
t_LHLL
5
t_AVLL
5
t_LLAX
5
t_LLIV
5
t_LLPL
5
t_PLPH
5
t_PLIV
5
t_PXIX
5
t_PXIZ
5
t_AVIV
5
t_PLAZ
5
Data Memory
Oscillator frequency: Speed Versions
S8XC550 Exx
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
3.5
16
85
2t_CLCL–40
7
t_CLCL–55
27
t_CLCL–35
150
4t_CLCL–100
22
t_CLCL–40
142
3t_CLCL–45
82
3t_CLCL–105
0
0
37
t_CLCL–25
207
5t_CLCL–105
10
10
t_RLRH
6, 7
t_WLWH
6, 7
t_RLDV
6, 7
t_RHDX
6, 7
t_RHDZ
6, 7
t_LLDV
6, 7
t_AVDV
6, 7
t_LLWL
6, 7
t_AVWL
6, 7
t_QVWX
6, 7
t_WHQX
6, 7
t_RLAZ
6, 7
t_WHLH
6, 7
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
275
6t_CLCL–100
275
6t_CLCL–100
212
5t_CLCL–165
0
0
55
2t_CLCL–70
350
8t_CLCL–150
397
9t_CLCL–165
137
247
3t_CLCL–50 3t_CLCL+50
120
4t_CLCL–130
12
t_CLCL–50
12
t_CLCL–50
0
0
22
102
t_CLCL–40
t_CLCL+40
t_CHCX
9
t_CLCX
9
t_CLCH
9
t_CHCL
9
Shift Register
High time
Low time
Rise time
Fall time
20
20
20
20
20
20
20
20
t_XLXL
8
Serial port clock cycle time
750
12t_CLCL
t_QVXH
8
Output data setup to clock rising edge
492
10t_CLCL–133
t_XHQX
8
Output data hold after clock rising edge
8
2t_CLCL–117
t_XHDX
8
Input data hold after clock rising edge
0
0
t_XHDV
8
Clock rising edge to input data valid
492
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
10t_CLCL–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1998 May 01
17