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80C550 Datasheet, PDF (15/28 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
Product specification
80C550/83C550/87C550
Electrical Deviations from Commercial Specifications for Extended Temperature Range
DC and AC parameters not included here are the same as in the commercial temperature range table.
DC ELECTRICAL CHARACTERISTICS
Tamb = –40°C to +85°C, VCC = 5V ±10% (87C550), VCC = 5V ±20% (80/83C550), VSS = 0V
TEST
SYMBOL
PARAMETER
CONDITIONS
VIL
Input low voltage, except EA
VIL1
Input low voltage to EA
VIH
Input high voltage, except XTAL1, RST
VIH1
Input high voltage to XTAL1, RST
IIL
Logical 0 input current, ports 2, 3
ITL
Logical 1-to-0 transition current, ports 2, 3
ICC
Power supply current:
Active mode
Idle mode
Power down mode
VIN = 0.45V
VIN = 2.0V
VCC = 4.5–5.5V,
Frequency range =
3.5 to 16MHz
LIMITS
MIN
MAX
–0.5
0
0.2VCC+1
0.7VCC+0.1
0.2VCC–0.15
0.2VCC–0.35
VCC+0.5
VCC+0.5
–75
–750
UNIT
V
V
V
V
µA
µA
35
mA
6
mA
50
µA
ADC DC ELECTRICAL CHARACTERISTICS
AVCC = 5V ±10%, AVSS = 0V, Tamb = –40°C to 85°C, unless otherwise specified
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
AVCC
VREF
AICC
AVIN
AIC, CIA
tADS
tADC
Ae
ERA
OSe
Analog supply
Analog reference; AVREF+ AVREF–
Analog operating supply current
Analog input voltage
Analog input capacitance
Sampling time
Conversion time
Absolute voltage error
Relative accuracy
Offset error
AVCC = VCC ± 0.2
See note 1
See note 1
4.5
5.5
V
AVSS – 0.2
AVCC + 0.2
V
3.0
mA
AVSS – 0.2
AVCC + 0.2
V
15
pF
8tCY
40tCY
±1.5
LSB
±1
LSB
±1
LSB
Ge
Gain error
See note 1
0.4
%
MCTC
Ct
Channel-to-channel matching
Crosstalk
0 – 100kHz
±1
LSB
–60
dB
Rref
Resistance between AVREF+ and AVREF–
1.0
10.0
KΩ
AIID
Idle mode supply current
See note 4
50
µA
AIPD
Power down supply current
See note 4
50
µA
NOTES:
1. Conditions: VREF+ = 4.99712V, VREF– = 0V. AICC value does not include the resistor ladder current. For the 40-pin package, where the
VREF– inputs are connected to AVCC and AVSS, the current AICC will be increased by the register ladder current and may exceed the
maximum shown here.
2. The resistor ladder network is not disconnected in the power-down or idle modes. Thus to conserve power, the user must remove AVCC and
VREF+.
3. If the A/D function is not required, or if the A/D function is only needed periodically, AVCC can be removed without affecting the operation of
the digital circuitry. Contents of ADCON and ADAT are not guaranteed to be valid. Digital inputs P1.0 to P1.7 will not function normally. No
digital outputs are present on these pins.
4. For this test, the Analog inputs must be at the supplies (either VDD or VSS).
1998 May 01
15