80C550 Datasheet, PDF (13/28 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
Product specification
80C550/83C550/87C550
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Block Diagram, page 3).
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals except the A/D stay active. the instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. An A/D conversion in
progress will be aborted when idle mode is entered. The CPU
contents, the on-chip RAM, and all of the special function registers
remain intact during this mode. The idle mode can be terminated
either by any enabled interrupt (at which time the process is picked
up at the interrupt service routine and continued), or by a hardware
reset which starts the processor in the same manner as a power-on
reset.
Programmable Idle Modes
The programmable idle modes have been dispersed throughout the
functional blocks. Each block has its own ability to be disabled. For
example, if timer 0 is not commanded to be running (TR = 0), then
the clock to the timer is disabled resulting in an idle mode power
saving. An additional idle control bit has been added to the serial
communications port.
A/D Operation in Idle Mode
When in the idle mode, the A/D converter will be disabled. However,
the current through the V_REF pins will be present and will not be
reduced internally in either the idle or the power-down modes. It is
the responsibility of the user to disconnect V_REF to reduce power
supply current.
MSB
PRE2 PRE1 PRE0 X
LSB
X WDRUN WDTOF WDMOD
BIT
SYMBOL
WDCON.7 PRE2
WDCON.6 PRE1
WDCON.5 PRE0
FUNCTION
Prescaler Select (Read/Write).
Prescaler Select (Read/Write).
Prescaler Select (Read/Write).
Thses bits select the prescaler divide ratio according to the following table:
PRE2
0
0
0
0
1
1
1
1
PRE1
0
0
1
1
0
0
1
1
PRE0
0
1
0
1
0
1
0
1
DIVISOR
(from f_OSC)
12 X 64
12 X 64 X 2
12 X 64 X 4
12 X 64 X 8
12 X 64 X 16
12 X 64 X 32
12 X 64 X 64
12 X 64 X 128
WDCON.4 —
WDCON.3 —
WDCON.2 WDRUN
WDCON.1 WDTOF
WDCON.0 WDMOD
Not used.
Not used.
Run Control (Read/Write).
This bit turns the timer on (WDRUN = 1) or off (WDRUN = 0) if the timer mode has been selected.
Timeout Flag (Read/Write).
This bit is set when the watchdog timer underflows. It is cleared by an external reset and can be
cleared by software.
Mode Selection (Read/Write).
When WDMOD = 1, the watchdog mode is selected; when WDMOD = 0, the timer mode is
selected. Selecting the watchdog mode automatically disables power-down mode. WDMOD is
cleared by external reset. Once the watchdog mode is selected, this bit can only be cleared by
writing a 0 to this bit and then performing a feed operation.
SU00200
Figure 4. Watchdog Control Register (WDCON)
1998 May 01
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