TDA5155 Datasheet, PDF(13/24 Page) NXP Semiconductors – Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

TDA5155 Datasheet, PDF (13/24 Pages) NXP Semiconductors – Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads

◁

Philips Semiconductors

Pre-ampliï¬er for Hard Disk Drive (HDD)

with MR-read/inductive write heads

Preliminary speciï¬cation

TDA5155

ADDRESS REGISTERS(1)

A7 A6 A5 A4 A3 A2 A1 A0

FUNCTION

0 X X X 0 0 1 1 MR current DAC register:

IMR = 0.5 Ã -1--R-0---e-k--x-â¦-t-- (10 + 16.d4 + 8.d3 + 4.d2 + 2.d1 + d0) mA

0 X X X 0 1 0 0 write current DAC register:

IWR = 1---R-0---e-k--x-â¦-t-- (20 + 16.d4 + 8.d3 + 4.d2 + 2.d1 + d0) mA

0 X X X 0 1 0 1 servo write register:

(d0,d1) = (0,0): one head

(d0,d1) = (1,1): all heads

(d0,d1) = (1,0): odd numbered heads (H1, H3, H5, H7 and H9)

(d0,d1) = (0,1): even numbered heads (H0, H2, H4, H6 and H8)

0 X X X 0 1 1 0 test mode register:

(d2,d1,d0) = (0,0,0) = not in test mode

(d2,d1,d0) = (0,0,1) = read head test (IMR1 = IMR2)

(d2,d1,d0) = (0,1,0) = read head test (IMR2 = 5 mA fixed)

(d2,d1,d0) = (0,1,1) = temperature monitor

(d2,d1,d0) = (1,X,d0) = thermal asperity detection, see note 2

Vth = (210 + 560.d0 + 280.d2) ÂµV

0 X X X 0 1 1 1 compensation capacitor register:

equivalent differential capacitance = (4.d2 + 2.d1 + 1.d0) Ã 2 pF

0 X X X 1 0 0 0 high frequency gain attenuator register

nominal pole frequency = 8----.--d----3----+-----4----.8--d-0---2-0---+--M---2--H-.---dz---1-----+-----1---.--d----0---

0 X X X 1 0 0 1 high frequency gain boost register

nominal zero frequency = 8----.--d----3----+-----4----.8--d-0---2-0---+--M---2--H-.---dz---1-----+-----1---.--d----0---

0 X X X 1 0 1 0 settle time register

settle time: tst = 2Âµs + -(---4---.--d----2-----+-----2---.--d----11-----+-----1---.--d----0-----+-----1---)--Âµs

1 X X X 1 1 1 1 device ID register

ID = 8.d3 + 4.d2 + 2.d1 + 1.d0; d3 to d0 are preset to (0,0,1,1)

1 X X X a3 a2 a1 a0 when a7 = 1, data from the register with address a3 to a0 is read out on

SDATA

Notes

1. Unused bits in the registers (indicated by X) are donât care. Default data, initialized at Power-up, is zero in all

registers. For VCC <2.5 V, the register contents are not guaranteed.

2. Vth programming uses both the test mode register and the compensation capacitor register. d0 in the formula above

is the LSB of the test mode register and d2 is the d2 data bit of the compensation capacitor register.

1997 Apr 08

▷