TDA5155 Datasheet, PDF (11/24 Pages) NXP Semiconductors – Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads

Philips Semiconductors
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
Preliminary specification
TDA5155
8.7 Operation of the serial interface
The serial interface programming is summarized in
Section 8.7.10.
8.7.1 CONFIGURATION
d0:
By default (d0 = logic 0), write data passes from the
write data input via the data flip-flop to the write driver.
The write driver toggles the current in the head at the
falling edges of:
V_data = ^V-----W----^D----^I-^x----⁽--^v--⁾----2^–----V----^W-----^D----^I-^y---⁽--^v---⁾- or
I_data = -I-^W-----^D----^I-^x---⁽--ⁱ--⁾---2^–-----I--^W----^D----^I-^y----⁽--ⁱ-⁾-
When d0 = logic 1, the write data flip-flop is not used.
The signal polarity is non-inverting from the inputs WDIx
and WDIy to the outputs nWx and nWy.
d1:
By default (d1 = logic 0), the pre-amplifier senses PECL
write signals at WDIx(v) and WDIy(v). When
d1 = logic 1, the pre-amplifier senses input write
currents at WDIx(i) and WDIy(i).
d2:
By default (d2 = logic 0), the write current is inhibited
under low supply voltage conditions. The write current
inhibit is made inactive by programming d2 to logic 1.
d3:
By default (d3 = logic 0), in write mode low supply
voltage, open head, and other conditions are monitored
and flagged at HUS. If d3 = logic 1, HUS is LOW in write
mode and HIGH in read mode.
d4:
The amplifier read gain may be programmed in the
configuration register. By default (d4 = logic 0), the read
gain is typically 160 with R_MR = 28 Ω. If d4 = logic 1, the
read amplifier gain is 3 dB higher (226 in this case).
d5:
In order to minimize the write-to-read recovery times,
the first stage of the read amplifier may be kept biased
during write mode. By default, (d5 = logic 0) the read
amplifier is powered down during write mode, and the
fast settling procedure is activated after write-to-read
switching. If d5 = logic 1 the read amplifier is kept biased
during write mode, and the fast settling procedure still
occurs if the head is changed or the MR current is
re-programmed.
8.7.2 POWER CONTROL
By default, d1 = d0 = logic 0, the pre-amplifier powers up
in sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1,
d0 = logic 0 the circuit goes in standby mode.
If d1 = d0 = logic 1, the circuit goes in active mode (read or
write mode depending on the R/W input).
8.7.3 HEAD SELECT
Selection of a wrong head (H10-H15) causes an head
unsafe condition. HUS goes HIGH when in write mode a
wrong head is selected and when d3 in the configuration
register is LOW. When in read mode and a wrong head is
selected, head H0 is therefore selected and if d3 in the
configuration register is LOW, HUS goes LOW.
8.7.4 SERVO WRITE
The circuit is prepared for servo writing. However, the
device will not be guaranteed.
8.7.5 TEST
d2 = d1 = d0 = logic 0. The circuit is not in test mode. This
is the default situation.
8.7.5.1 MR head test
d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the
voltages at Rx and Ry (at the top of the MR elements) of
the selected head are fed to outputs RDx and RDy.
By measuring the output voltages single ended at two
different I_MR currents, the MR resistance can be accurately
measured according to the following formula:
R_MRx = ^V--I--_M-^R---^DR----^xx--¹¹----^––-----VI--_M--^R--_R--^D-_x--^x-₂--²- for the x-side.
Open head and head short-circuited-to-ground conditions
can therefore be detected.
d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before,
with the difference that I_MR2 is fixed to a minimum constant
value of 5 mA. Measuring in the same way as above with
I_MR1 > 5 mA, enables the detection of MR elements
shorted together.
8.7.5.2 Temperature monitor
d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature
monitor voltages are connected to RDx and RDy.
The output differential voltage depends on the
temperature according to: dV = −0.00364 × T + 1.7;
0 < T < 140 °C. The temperature may be measured with a
typical precision of 5 °C.
1997 Apr 08
11