PHT6NQ10T Datasheet, PDF (1/7 Pages) NXP Semiconductors – N-channel TrenchMOS transistor

Philips Semiconductors
N-channel TrenchMOS™ transistor
Product specification
PHT6NQ10T
FEATURES
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
g
s
QUICK REFERENCE DATA
V_DSS = 100 V
I_D = 6.5 A
R_DS(ON) ≤ 90 mΩ
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect transistor in a plastic
envelope
using
’trench’
technology.
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
The PHT6NQ10T is supplied in the
SOT223 surface mounting
package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
SOT223
4
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
I_D
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
T_j = 25 ˚C to 150˚C
T_j = 25 ˚C to 150˚C; R_GS = 20 kΩ
Continuous drain current (dc) T_sp = 25 ˚C
T_amb = 25 ˚C
Continuous drain current (dc) T_sp = 100 ˚C
T_amb = 100 ˚C
Pulsed drain current
Total power dissipation
Operating junction and
T_sp = 25 ˚C
T_amb = 25 ˚C
storage temperature
MIN.
-
-
-
-
-
-
-
-
-
-
- 65
MAX.
100
100
± 20
6.5
3
4.1
1.9
26
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL
R_{th j-sp}
R_{th j-amb}
PARAMETER
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
CONDITIONS
surface mounted, FR4
board
surface mounted, FR4
board
TYP.
12
70
MAX.
15
-
UNIT
K/W
K/W
August 1999
1
Rev 1.000